VLSI memory technology: Current status and future trends

European Solid-State Circuits Conference

Volumn , Issue , 1999, Pages 3-10

  Itoh, Kiyoo ^a   Kimura, Shin'ichiro ^a   Sakata, Takeshi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELL CAPACITANCE; MEMORY TECHNOLOGY; PACKET PROTOCOLS; REDUCING PROCESS; SUB-THRESHOLD CURRENT; SUBSYSTEM TECHNOLOGY; SYNCHRONOUS OPERATIONS; TECHNOLOGY TRENDS;

FLASH MEMORY; MEMORY ARCHITECTURE; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84888020839     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (43)

1. T. Kirihata et al., "A 390mmsup2/sup 16 Bank 1Gb DDR SDRAM with Hybrid Bitline Architecture, " ISSCC99 Dig. Tech. Papers, pp. 420-421, Feb. 1999.
2. S. Takase and N. Kushiyama, "A 1.6GB/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme, " ISSCC99 Dig. Tech. Papers, pp. 410-411, Feb. 1999.
3. For example, SRAM chips in ISSCC99 Dig. Tech. Papers, Feb. 1999.
4. For example, 16-Mb SRAM chips in ISSCC 92 Dig. Tech. Papers, Feb 1992.
5. A.Nozoe et al., "A 256Mb Multilevel Flash Memory with 2MB/s Program Rate for Mass Storage Applications, " ISSCC99 Dig. Tech. Papers, pp.110-111, Feb. 1999.
6. K. Imamiya et al., "A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology, " ISSCC99 Dig. Tech. Papers, pp.112-113, Feb. 1999.
7. For example, T. Miyakawa et al., "A 0.5|im 3V 1T1C 1Mb FRAM with a Variable Reference Bitline Voltage Scheme using a Fatigue-Free Reference Capacitor, " ISSCC99 Dig. Tech. Papers, pp. 104-105, Feb. 1999.
8. S. S. Iyer and H. L. Kalter, "Embedded DRAM technology, " IEEE SPECTRUM, pp.56-64, April 1999.
9. K. Itoh et al., "Trends in low-power RAM circuit technologies, " Proc. IEEE, vol. 83, No.4, pp.524-543, Apr. 1995.
10. K. Itoh et al., "Limitations and challenges of multigigabit DRAM chip design, " IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 624-634, May 1997.
11. K. Itoh et al., "Ultralow-Voltage Memory Circuits, " VLSI'97 Tutorial, Gramado (Brazil), Aug. 1997.
12. K. Itoh, "Pathways to DRAM Design and Technology for the 21st Century, " Electrochemical Society Proc, vol. 98-1, pp.350-369, 1998.
13. Edited by Semiconductor Industry Association, "The National Technology Roadmap for Semiconductors, " 1997 edition.
14. M. Koyanagi et al., "Novel High Density, Stacked Capacitor MOS RAM, " IEDM Tech. Dig., p. 348, 1978.
15. H. Sunami et al., "A Corrugated Capacitor Cell (CCC), " IEEE Trans. Electron Devices, vol. ED-31, p. 746, 1984.
16. Y. Ohji et al., "Reliability of Nano-Meter Thick Multi-Layer Dielectric Films on poly-Crystalline Silicon, " Tech. Dig. of International Reliability Physics Symposium, p. 55, 1987.
17. T. Kisu et al., "A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell, " Ext. Abstract, 20th Conf. On Solid State Devices and Materials, p. 581, 1988.
18. S. Kimura et al., "A Diagonal Active-Area Stacked Capacitor DRAM Cell with Storage Capacitor on Bit-Line, " IEEE Trans. Electron Devices, vol. 37, No.3, p. 737, 1990.
19. M. Sakao et al., "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs, " IEDM Tech. Dig., p. 655, 1990.
20. I. Asano et al., "1.5nm Equivalent Thickness Ta205 High-k Dielectric with Rugged Si Suited for Mass Production of High Density DRAMs, " IEDM Tech. Dig., p. 755, 1998.
21. H. Shinriki et al., "Promising Storage Capacitor Structures with Thin Ta205 Films for Low-Power High-Density DRAM's, " IEEE Trans. Electron Devices, ED-37, p. 1939, 1990.
22. H. Watanabe et al., "A New Cylindrical Capacitor using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs, " IEDM Tech. Dig., p.259, 1992.
23. K. Ono et al., "(Ba, Sr)Ti03 Capacitor Technology for Gbit-Scale DRAMs, " IEDM Tech. Dig., p.803, 1998.
24. K. Sunouchi et al., "Process Integration for 64M DRAM using an Asymmetrical Stacked Trench Capacitor (AST) Cell, " IEDM Tech. Dig., p.647, 1990
25. G. Bronner et al., "A Fully Planarized 0.25nm CMOS Technology for 256Mbit DRAM and Beyond, " Dig. Tech. Papers, 1995 symp. VLSI Technology, p. 15, 1995.
26. H. Ishiuchi et al., "Embedded DRAM Technologies, " 1995 symp. VLSI Technology, p. 33, 1997.
27. H.-J. Yoo et al., "A 150MHz 8-banks 256M Synchronous DRAM with Wave Pipelining Methods, " ISSCC95 Dig. Tech. Papers, pp. 250-251, Feb. 1995.
28. T. Saeki et al., "A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay, " ISSCC96 Dig. Tech. Papers, pp. 374-375, Feb. 1996.
29. H. Yoon et al., "A 2.5V 333Mb/s/pin 1Gb Double Data Rate SDRAM, " ISSCC99 Dig. Tech. Papers, pp. 412-413, Feb. 1999.
30. Y. Takai et al., "A 250Mb/s/pin 1Gb Double Data Rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme, " ISSCC99 Dig. Tech. Papers, pp. 418-419, Feb. 1999.
31. P. Gillingham and B. Vogley, "SLDRAM: High-performance, open-standard memory, " IEEE Micro, pp. 29-39, Nov./Dec. 1997.
32. Y. Nakase et al., "Source-Synchronization and Timing Vernier Techniques for 1.2-GB/s SLDRAM Interface, " IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 494-501, Apr. 1999.
33. L. Paris et al., "A 800MB/s 72Mb SLDRAM with Digitally Calibrated DLL, " ISSCC99 Dig. Tech. Papers, pp. 416-417, Feb. 1999.
34. R. Crisp, "Direct Rambus technology: The new main memory standard, " IEEE Micro, pp. 18-28, Nov./Dec. 1997.
35. Y. Konishi et al., "Interface Technologies for Memories and ASICs-Review and Future Direction-, " IEICE Trans. Electron., vol. E82-C, no. 3, pp. 438-447, Mar. 1999.
36. T.Shimizu et al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM, " ISSCC96 Dig. Tech. Papers, pp.216-217, Feb. 1996.
37. T. Kimura et al., "64Mb 6.8ns Random ROW Access DRAM Macro for ASICs, " ISSCC99 Dig. Tech. Papers, pp.416-417, Feb. 1999.
38. I. Naritake et al., "A 12ns 8MB DRAM Secondary Cache for a 64b Microprocessor, " ISSCC99 Dig. Tech. Papers, pp.420-421, Feb. 1999.
39. M. Hasegawa et al., "A 256Mb SDRAM with Subthreshold Leakage Current Suppression, " ISSCC98 Dig. Tech. Papers, pp.80-81, Feb. 1998.
40. H. Mizuno et al., "A 18uA-Standy-Current 1.8V 200MHz Microprocessor with Self Substrate-Biased Data-Retention Mode, " ISSCC99 Dig. Tech. Papers, pp.280-281, Feb. 1999.
41. K. Yano et al., "A 128Mb Early Prototype for Gigascale Single Electron Memories, " ISSCC98 Dig. Tech. Papers. pp.344-345, Feb. 1998.
42. K. Nakazato et al., "Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cells, " ELECTRONICS LETTERS vol.35, No. 10, pp.848-850, 13th May 1999.
43. H. Nambu et al., "A 550-ps Access, 900-MHz, 1-Mb ECL-CMOS SRAM, " Symp. VLSI Circuits, June 1999.