Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cells

Electronics Letters

Volumn 35, Issue 10, 1999, Pages 848-850

  Nakazato, K ^a   Itoh, K ^b   Mizuta, H ^a   Ahmed, H ^c  

^a HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

^b HITACHI LTD   (Japan)

^c UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICA;

SILICON STACKED TUNNEL TRANSISTORS;

MOSFET DEVICES;

EID: 0032625243     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19990574     Document Type: Article

References (4)

1. NAKAZATO, K., PIOTROWICZ, P.J.A., HASKO, D.G., AHMED, H., and ITOH, K.: 'PLED - Planar localised electron devices', IEDM 97, 1997, pp. 179-182
2. MIZUTA, H., NAKAZATO, K., PIOTROWICZ, P.J.A., ITOH, K., TESHIMA, T., YAMAGUCHI, K., and SHIMADA, T.: 'Normally-off PLED (planar localised electron device) for non-volatile memory', VLSI Symp., 1998
3. 2 for VLSI', IEEE Trans., 1985, ED-32, pp. 106-123
4. SUZUKI, K., TANAKA, T., TOSAKA, Y., HORIE, H., and ARIMOTO, Y.: 'Scaling theory for double-gate SOI MOSFETs', IEEE Trans. Electron Dev., 1993, ED-40, pp. 2326-2329