An efficient synchronization technique for multiprocessor systems on-chip

Proceedings of the 2005 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA 2005

Volumn , Issue , 2005, Pages 33-40

  Monchiero, Matteo ^a   Palermo, Gianluca ^a   Silvano, Cristina ^a   Villa, Oreste ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY CONSERVATION; FAULT TOLERANCE; MEMORY ARCHITECTURE; NETWORK-ON-CHIP; SYNCHRONIZATION; SYSTEM-ON-CHIP;

EXPERIMENTAL VALIDATIONS; MULTIPROCESSOR SYSTEMS ON CHIPS; OPTIMIZATION TECHNIQUES; SIMULATION PLATFORM; SYNCHRONIZATION MECHANISMS; SYNCHRONIZATION OPERATION; SYNCHRONIZATION TECHNIQUE; TARGET ARCHITECTURES;

NETWORK ARCHITECTURE;

EID: 84887442541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1152779.1147357     Document Type: Conference Paper

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