Gate-level mitigation techniques for neutron-induced soft error rate

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 175-180

  Deogun, Harmander Singh ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL LOGIC; CROSS-COUPLED; MITIGATION TECHNIQUES; OPERATING VOLTAGE; PROBABILITY-BASED ANALYSIS; PROCESS TECHNOLOGIES; SINGLE EVENT UPSETS; SOFT ERROR RATE;

ERROR CORRECTION;

MICROPROCESSOR CHIPS;

EID: 84886656719     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.61     Document Type: Conference Paper

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