Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2013, Pages 83-88

  Lorente, Vicente ^a   Valero, Alejandro ^a   Sahuquillo, Julio ^a   Petit, Salvador ^a   Canal, Ramon ^b   López, Pedro ^a   Duato, José ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; CACHE MEMORY; ECONOMIC AND SOCIAL EFFECTS; ENERGY CONSERVATION; ERRORS;

DYNAMIC ENERGY; ENERGY BUDGETS; FAILURE PROBABILITY; FAULT COVERAGES; FAULT-TOLERANT; LOW POWER MODES; MODERN MICROPROCESSOR; SUPPLY VOLTAGES;

STATIC RANDOM ACCESS STORAGE;

EID: 84885663644     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2013.031     Document Type: Conference Paper

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