An hybrid eDRAM/SRAM macrocell to implement first-level data caches

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 213-221

  Valero, Alejandro ^a   Sahuquillo, Julio ^a   Petit, Salvador ^a   Lorente, Vicente ^a   Canal, Ramon ^b   López, Pedro ^a   Duato, José ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Leakage current; Retention time; Static and dynamic memory cells

Indexed keywords

DATA CACHES; DRAM CELLS; LEAKAGE ENERGIES; MACRO CELLS; MEMORY CELL; RETENTION TIME; SET-ASSOCIATIVE; SET-ASSOCIATIVE CACHES; SPEED LIMIT; SRAM CELL; STATIC AND DYNAMIC; STATIC AND DYNAMIC MEMORY CELLS; WRITE-BACK;

CACHE MEMORY; CYTOLOGY; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC LOAD SHEDDING; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE;

CELLS;

EID: 76749128041     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669140     Document Type: Conference Paper

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