An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2013, Pages 1248-1251

  Ma, Yitao ^a   Shibata, Tadashi ^b   Endoh, Tetsuo ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-SPEED LOW-POWER; HIGHER DIMENSIONS; HYBRID TECHNOLOGY; MAGNETIC TUNNEL JUNCTION; NONVOLATILE MEMORY CELLS; PROPOSED ARCHITECTURES; SPEED PERFORMANCE; SPICE SIMULATIONS;

ASSOCIATIVE PROCESSING; ASSOCIATIVE STORAGE; MAGNETIC DEVICES; SPICE; STATIC RANDOM ACCESS STORAGE;

MEMORY ARCHITECTURE;

EID: 84883428485     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2013.6572079     Document Type: Conference Paper

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