A real-time image recognition system using a global directional-edge- feature extraction VLSI processor

ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 248-251

  Zhu, Hongbo ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC ADAPTATION; FEATURE VECTORS; FEATURE-BASED; IMAGE CAPTURES; IMAGE DATA; PROCESSING SPEED; REAL-TIME IMAGES; TIME-CRITICAL APPLICATIONS; VLSI PROCESSORS;

DATA TRANSFER; DELAY CIRCUITS; DIGITAL CIRCUITS; EMBEDDED SYSTEMS; IMAGE RECOGNITION; MICROPROCESSOR CHIPS; MILITARY PHOTOGRAPHY; SENSORS; VLSI CIRCUITS;

FEATURE EXTRACTION;

EID: 72849121834     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2009.5325996     Document Type: Conference Paper

References (11)

1. R. Karakiewicz, R. Genov and G. Cauwenberghs, 480-GMACS/mW resonant adiabatic mixed-signal processor array for charge-based pattern recognition, IEEE J. Solid-State Circuits, Vol. 42, No. 11, pp. 2573-2584, 2007.
2. G. M. Bo, D. D. Caviglia and M. Valle, An analog VLSI implementation of a feature extractor for real time optical character recognition, IEEE J. Solid-State Circuits, Vol. 33, No. 4, pp. 556-564, 1998.
3. 2 20-mW real-time face detection core, IEEE J. Solid-State Circuits, Vol. 42, No. 4, pp. 790-797, 2007.
4. K. Kim, S. Lee, J. Kim, M. Kim and H. Yoo, A 125 GOPS 583 mW Network-on-Chip based parallel processor with bio-inspired visual attention engine, IEEE J. Solid-State Circuits, Vol. 44, No. 1, pp. 136-147, 2009.
5. G. H. Hubel and T. N. Wiesel, Receptive fields of single neurones in the cat's striate cortex, J. Physiol., Vol. 148, pp. 574-591, 1959.
6. M. Yagi and T. Shibata, An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems, IEEE Trans. Neural Networks, Vol. 14, No. 5, pp. 1144-1161, 2003.
7. H. Yamasaki and T. Shibata, A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture, IEEE J. Solid-State Circuits, Vol. 42, No. 9, pp. 2046-2053, 2007.
8. M. Ogawa and T. Shibata, A delay-encoding-logic array processor for dynamic-programming matching of data sequences, IEEE J. Solid-State Circuits, Vol. 40, No. 7, pp. 1578-1582, 2005.
9. H. Zhu and T. Shibata, A digital-pixel-sensor-based global feature extraction VLSI for real-time image recognition, International Conference on Solid State Devices and Materials (SSDM), pp. 476-477, Tsukuba, Japan, Sep. 24-26, 2008.
10. H. Zhu and T. Shibata, A digital-pixel-sensor-based global feature extraction processor for real-time object recognition, Jpn. J. Appl. Phys., Vol. 48, No. 4, pp. 04C080-1-7, 2009.
11. K. Ito, B. Tongprasit and T. Shibata, A computational digital pixel sensor featuring block-readout architecture for on-chip image processing, IEEE Trans. Circuits Syst.-I, Vol. 56, No. 1, pp. 114-123, 2009.