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Volumn , Issue , 2013, Pages 885-890

Development and characterization of a through-multilayer TSV integrated SRAM module

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS BUS; CMP PROCESS; COATING TECHNOLOGIES; DOUBLE LAYERS; INTEGRATION PROCESS; LIFT-OFF PROCESS; MEMORY CHIPS; VIA FILLING;

EID: 84883395839     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2013.6575678     Document Type: Conference Paper
Times cited : (9)

References (10)
  • 1
    • 24644517630 scopus 로고    scopus 로고
    • Architectural implications and process development of 3-d vlsi z-axis interconnectsusing through silicon vias
    • L. Schaper, "Architectural Implications and Process Development of 3-D VLSI Z-Axis InterconnectsUsing Through Silicon Vias," IEEE Transactions on Advanced Package, vol. 28, no.3, pp. 355-365, 2005
    • (2005) IEEE Transactions on Advanced Package , vol.28 , Issue.3 , pp. 355-365
    • Schaper, L.1
  • 3
    • 61649110276 scopus 로고    scopus 로고
    • Three-dimensional silicon integration
    • J. U. Knickerbocker, "Three-dimensional silicon integration," IBM J. Res. & Dev., vol. 52, no. 6, pp. 553-570, 2008
    • (2008) IBM J. Res. & Dev. , vol.52 , Issue.6 , pp. 553-570
    • Knickerbocker, J.U.1
  • 4
    • 73249131982 scopus 로고    scopus 로고
    • 8 gb 3-d ddr3 dram using through-silicon-via technology
    • U. Kang, "8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology," IEEE Journal of Solid-State Circuits, vol. 45, pp. 111-119, 2010
    • (2010) IEEE Journal of Solid-State Circuits , vol.45 , pp. 111-119
    • Kang, U.1
  • 5
    • 84866869533 scopus 로고    scopus 로고
    • Design and process development of a stacked sram memory chip module with tsv interconnection
    • S. L. Ma, "Design and Process Development of a Stacked SRAM Memory Chip Module with TSV Interconnection," IEEE Electronic Components and Technology Conference (ECTC), pp. 1925-1929, 2012
    • (2012) IEEE Electronic Components and Technology Conference (ECTC) , pp. 1925-1929
    • Ma, S.L.1
  • 7
    • 77950941006 scopus 로고    scopus 로고
    • Bottom-up filling of through silicon via (tsv) with parylene as sidewall protection layer
    • M. Miao, M., "Bottom-up Filling of Through Silicon Via (TSV) with Parylene as Sidewall Protection Layer", Electronics Packaging Technology Conference (EPTC), pp. 442-446, 2009
    • (2009) Electronics Packaging Technology Conference (EPTC) , pp. 442-446
    • Miao, M.1
  • 8
    • 77955188264 scopus 로고    scopus 로고
    • Development of cmos-process-compatible interconnect technology for 3d-stacking of nand flash memory chips
    • X. Q. Shi, "Development of CMOS-process-compatible interconnect technology for 3D-stacking of NAND flash memory chips," IEEE Electronic Components and Technology Conference (ECTC), pp. 74-78, 2010
    • (2010) IEEE Electronic Components and Technology Conference (ECTC) , pp. 74-78
    • Shi, X.Q.1
  • 10
    • 84655163339 scopus 로고    scopus 로고
    • A 1.2 v 12.8 gb/s 2 gb mobile wide-i/o dram with 4 128 i/os using tsv based stacking
    • J. S. Kim, "A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking," IEEE Jouranl of Solid-State Circuits, vol. 47, pp. 107-116, 2012.
    • (2012) IEEE Jouranl of Solid-State Circuits , vol.47 , pp. 107-116
    • Kim, J.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.