MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2013, Pages 105-108

  Natsui, Masanori ^a   Hanyu, Takahiro ^a   Sakimura, Noboru ^b   Sugibayashi, Tadahiko ^b  

^a TOHOKU UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELL-BASED DESIGN; DESIGN FLOWS; DESIGN TOOL; DEVICE MODELING; LOGIC IN MEMORY; LOGIC-IN-MEMORY ARCHITECTURE; NON-VOLATILE; PATTERN LAYOUT;

INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; MEMORY ARCHITECTURE;

LOGIC CIRCUITS;

EID: 84883361245     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2013.6571793     Document Type: Conference Paper

References (9)

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