Variation-resilient current-mode logic circuit design using MTJ devices

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2012, Pages 2705-2708

  Kim, Youngkeun ^a   Natsui, Masanori ^a   Hanyu, Takahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; COMPENSATING ELEMENT; CURRENT MODE; CURRENT MODE LOGIC; HSPICE SIMULATIONS; PERFORMANCE CAPABILITY; RESISTANCE VALUES; VLSI PROCESSORS;

CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; MOS DEVICES; SPICE; VLSI CIRCUITS;

LOGIC CIRCUITS;

EID: 84866603530     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2012.6271866     Document Type: Conference Paper

References (12)

1. T. Tsunomura, A. Nishida and T. Hiramoto,"Verification of threshold voltage variation of scaled transistors with ultralarge-scale device matrix array test element group," Jpn. J. Appl. Phys., vol. 48, no. 12, p. 124505, 2009.
2. http://www. itrs. net
3. K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara and T. Hiramoto,"Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies," IEDM Tech. Dig., Dec. 2007, pp. 467-470.
4. S. Ikeda, J. Hayakawa, Y. M. Lee, F. Matsukura, Y. Ohno, T. Hanyu, and H. Ohno,"Magnetic Tunnel Junctions for Spintronic Memories and Beyond," IEEE Trans. Electron Devices, vol. 54, no. 05, pp. 991-1002, 2007.
5. S. Matsunaga, K. Hiyama, A. Matsumoto, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh H. Ohno, and T. Hanyu,"Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices," Applied Physics Express (APEX), vol. 2, no. 2, pp. 023004-1-023004-3, 2009.
6. D. Suzuki, M. Natsui, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu,"Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array," IEEE 2009 Symposia on VLSI Circuits, Dig. Tech. Papers, pp. 80-81, 2009.
7. M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, and H. Yamada,"A GHz MOS adaptive pipeline technique using MOS current-mode logic," IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 784-791, 1996.
8. M. Alioto and G. Palumbo,"Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework," IEEE Circuits Syst. Mag., vol. 6, no. 4, pp. 40-59, 2006.
9. A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara and H. Sakuraba,"0. 18-?m CMOS 10-Gbs/s Multiplexer/Demulitiplexer ICs Using Current Mode logic with Tolerance to Threshold Voltage Fluctuation," IEEE J. Solid-state Circuits, Vol 36, no. 6, pp. 988-996, 2001.
10. S. Ikeda, K. Miura, H. Yamamoto, K. Mizunuma, H. D. Gan, M. Endo, S. Kanai, J. Hayakawa, F. Matsukura, and H. Ohno,"A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction," Nature Mater. Vol. 9, pp. 721-724, 2010.
11. T. Kawahara, R. Takemura, K. Miura, J. Hayakawa, S. Ikeda, Y. M. Lee, R. Sasaki, Y. Goto, K. Ito, T. Meguro, F. Matsukura, H. Takahashi, H. Matsuoka, and H. Ohno,"2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read," IEEE J. Solid-State Circuits vol. 43, no. 1 pp. 109-120, 2008.
12. M. Natsui and T. Hanyu,"Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact," 19th International Workshop on Post-Binary ULSI Systems, pp. 20-25, 2010.