STREX: Boosting instruction cache reuse in OLTP workloads through stratified transaction execution

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 273-284

  Atta, Islam ^a   Tözün, Pinar ^b   Tong, Xin ^a   Ailamaki, Anastasia ^b   Moshovos, Andreas ^a  

^a EPFL   (Switzerland)

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

Instruction cache; Instruction locality; OLTP; Thread scheduling

Indexed keywords

INSTRUCTION CACHES; INSTRUCTION LOCALITY; INSTRUCTION REUSE; OLTP; ONLINE TRANSACTION PROCESSING; PERFORMANCE BENEFITS; THREAD SCHEDULING; TRANSACTION EXECUTION;

COMPUTER ARCHITECTURE;

CACHE MEMORY;

EID: 84881177627     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485946     Document Type: Conference Paper

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