PALM: Parallel architecture-friendly latch-free modifications to B+ trees on many-core processors

Proceedings of the VLDB Endowment

Volumn 4, Issue 11, 2011, Pages 795-806

  Sewall, Jason ^a   Chhugani, Jatin ^a   Kim, Changkyu ^a   Satish, Nadathur ^a   Dubey, Pradeep ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORESTRY; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES;

B TREES; BULK SYNCHRONOUS PARALLEL MODEL; CURRENT PROCESSORS; MANY-CORE PROCESSORS; NOVEL TECHNIQUES; ON CURRENTS; ON-CURRENTS; POINT-TO-POINT COMMUNICATION; SCALABLE LATCH; THREAD LEVEL PARALLELISM;

CONCURRENCY CONTROL;

AUTOMATIC CONTROL; COMPUTER PROGRAMING; PROCESS VARIABLES; RESPONSE TIME; THROUGHPUT;

EID: 84860598151     PISSN: None     EISSN: 21508097     Source Type: Journal    
DOI: 10.14778/3402707.3402719     Document Type: Conference Paper

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