Improving instruction cache performance in OLTP

ACM Transactions on Database Systems

Volumn 31, Issue 3, 2006, Pages 887-920

  Harizopoulos, Stavros ^a   Ailamaki, Anastassia ^b,c  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c Carnegie Mellon University   (United States)

Author keywords

Cache misses; Instruction cache

Indexed keywords

CACHE MISSES; INSTRUCTION CACHE; RESEARCH PROTOTYPE DATABASE SYSTEMS; SYNCHRONIZATION BARRIERS;

COMPUTER SOFTWARE; DATABASE SYSTEMS; MICROPROCESSOR CHIPS; PRODUCT DESIGN; PROGRAM PROCESSORS; RAPID PROTOTYPING;

CACHE MEMORY;

EID: 33750190611     PISSN: 03625915     EISSN: 03625915     Source Type: Journal    
DOI: 10.1145/1166074.1166079     Document Type: Conference Paper

References (30)

1. AILAMAKI, A., DEWITT, D. J., HILL, M. D., AND SKOUNAKIS, M. 2001a. Weaving relations for cache performance. In VLDB '01: Proceedings of the 27th International Conference on Very Large Data Bases. Morgan Kaufmann, San Francisco, CA, 169-180.
2. AILAMAKI, A., DEWITT, D. J., AND HILL, M. D. 2001b. Walking four machines by the shore. In Proceedings of the Fourth Workshop on Computer Architecture Evaluation Using Commercial Workloads (CAECW).
3. AILAMAKI, A., DEWITT, D. J., HILL, M. D., AND WOOD, D. A. 1999. DBMSs on a modern processor: Where does time go? In VLDB '99: Proceedings of the 25th International Conference on Very Large Data Bases. Morgan Kaufmann, San Francisco, CA, 266-277.
4. ANNAVARAM, M., PATEL, J. M., AND DAVIDSON, E. S. 2003. Call graph prefetching for database applications. ACM Trans. Comput. Syst. 21, 4, 412-444.
5. BARROSO, L. A., GHARACHORLOO, K., AND BUONION, E. 1998. Memory system characterization of commercial workloads. In ISCA '95: Proceedings of the 25th Annual International Symposium on Computer Architecture, IEEE Computer Society Press, Los Alamitos, CA, 3-14.
6. BROWNE, S., DEANE, C., Ho, G., AND MUCCI, P. 1999. PAPI: A portable interface to hardware performance counters. In Proceedings of Department of Defense HPCMP Users Group Conference.
7. CAREY, M. J., DEWITT, D. J., FRANKLIN, M. J., HALL, N. E., MCAULIFFE, M. L., NAUGHTON, J. F., SCHUH, D. T., SOLOMON, M. H., TAN, C. K., TSATALOS, O. G., WHITE, S. J., AND ZWILLING, M. J. 1994. Shoring up persistent applications. In SIGMOD '94: Proceedings of the 1994 ACM SIGMOD International Conference on Management of Data. ACM Press, New York, NY, 383-394.
8. CHEN, I.-C. K., LEE, C.-C., AND MUDGE, T. N. 1997. Instruction prefetching using branch prediction information. In ICCD '97: Proceedings of the 1997 International Conference on Computer Design (ICCD '97). IEEE Computer Society Press, Los Alamitos, CA, 593.
9. CHILIMBI, T. M., HILL, M. D., AND LARUS, J. R. 2000. Making pointer-based data structures cache conscious. Computer 33, 12, 67-74.
10. GRAEFE, G. AND LAESON, P. 2001. B-tree indexes and CPU caches. In Proceedings of the 17th International Conference on Data Engineering. IEEE Computer Society Press, Los Alamitos, CA, 349-358.
11. HARDAVELLAS, N., SOMOGYI, S., WENISCH, T. F., WUNDERLICH, R. E., CHEN, S., KIM, J., FALSAFI, B., HOE, J. C., AND NOWATZYK, A. G. 2004. Simflex: A fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Perform. Eval. Rev. 31, 4, 31-34.
12. HARIZOPOULOS, S. AND AILAMAKI, A. 2004. STEPS towards cache-resident transaction processing. In VLDB '04: Proceedings of the 30th International Conference on Very Large Data Bases. Morgan Kaufmann, San Francisco, CA, 660-671.
13. HENNESSY, J. L. AND PATTERSON, D. A. 1996. Computer Architecture: A Quantitative Approach (2nd ed.). Morgan Kaufmann, San Francisco, CA.
14. JAYASIMHA, J. AND KUMAR, A. 1999. Thread-based cache analysis of a modified TPC-C workload. In Proceedings of the Second Workshop on Computer Architecture Evaluation Using Commercial Workloads.
15. KEETON, K., PATTERSON, D. A., HE, Y. Q., RAPHAEL, R. C., AND BAKER, W. E. 1998. Performance characterization of a quad pentium pro smp using oltp workloads. In ISCA '98: Proceedings of the 25th Annual International Symposium on Computer Architecture. IEEE Computer Society Press, Los Alamitos, CA, 15-26.
16. Lo, J. L., BARROSO, L. A., EGGERS, S. J., GHARACHORLOO, K., LEVY, H. M., AND PAREKH, S. S. 1998. An analysis of database workload performance on simultaneous multithreaded processors. In ISCA '98: Proceedings of the 26th Annual International Symposium on Computer Architecture. IEEE Computer Society Press, Los Alamitos, CA, 39-50.
17. MAGNUSSON, P. S., CHRISTENSSON, M., ESKILSON, J., FORSGREN, D., HLLBERG, G., HGBERG, J., LARSSON, F., MOESTEDT, A., AND WERNER, B. 2002. Simics: A full system simulation platform. Computer 35, 2, 50-58.
18. MAYNARD, A. M. G., DONNELLY, C. M., AND OLSZEWSKI, B. R. 1994. Contrasting characteristics and cache performance of technical and multiuser commercial workloads. In ASPLOS-VI: Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems. ACM Press, New York, NY, 145-156.
19. PADMANABHAN, S., MALKEMUS, T., AGARWAL, R. C., AND JHINGRAN, A. 2001. Block oriented processing of relational database operations in modern computer architectures. In Proceedings of the 17th International Conference on Data Engineering. IEEE Computer Society Press, Los Alamitos, CA, 567-574.
20. RAMIREZ, A., BARROSO, L. A., GHARACHOHLOO, K., COHN, R., LARRIBA-PEY, J., LOWNEY, P. G., AND VALERO, M. 2001. Code layout optimizations for transaction processing workloads. In ISCA '01: Proceedings of the 28th Annual International Symposium on Computer Architecture, ACM Press, New York, NY, 155-164.
21. RANGANATHAN, P., GHARACHORLOO, K., ADVE, S. V., AND BARROSO, L. A. 1998. Performance of database workloads on shared-memory systems with out-of-order processors. In ASPLOS-VIII: Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems. ACM Press, New York, NY, 307-318.
22. ROMER, T., VOELKEH, G., LEE, D., WOLMAN, A., WONG, W., LEVY, H., BEHSHAD, B., AND CHEN, B. 1997. Instrumentation and optimization of win32/intel executables using etch. In Proceedings of the USENIX Windows NT Workshop.
23. ROSENBLUM, M., BUGNION, E., HERHOD, S. A., WITCHEL, E., AND GUPTA, A. 1995. The impact of architectural trends on operating system performance. In SOSP '95: Proceedings of the Fifteenth ACM Symposium on Operating Systems Principles. ACM Press, New York, NY, 285-298.
24. ROTENBERG, E., BENNETT, S., AND SMITH., J. E. 1996. Trace cache: A low latency approach to high bandwidth instruction fetching. In MICRO 29: Proceedings of the 29th Annual ACM / IEEE International Symposium on Microarchitecture. IEEE Computer Society Press, Los Alamitos, CA, 24-35.
25. SAVAGE, S., BURROWS, M., NELSON, G., SOBALVARHO, P., AND ANDEHSON, T. 1997. Eraser: A dynamic data race detector for multithreaded programs. ACM Trans. Comput. Syst. 15, 4, 391-411.
26. SHAO, M., AILAMAKI, A., AND FALSAFI, B. 2005. DBmbench: Fast and accurate database workload representation on modern microarchitecture. In Proceedings of the 15th IBM Center for Advanced Studies Conference (Oct).
27. SHATDAL, A., KANT, C., AND NAUGHTON, J. F. 1994. Cache conscious algorithms for relational query processing. In VLDB '94: Proceedings of the 20th International Conference on Very Large Data Bases. Morgan Kaufmann, San Francisco, CA, 510-521.
28. SRIVASTAVA, A. AND EUSTACE, A. 1994. Atom: A system for building customized program analysis tools. In PLDI '94: Proceedings of the ACM SIGPLAN 1994 Conference on Programming Language Design and Implementation. ACM Press, New York, NY, 196-205.
29. STETS, R., GHABACHOHLOO, K., AND BARHOSO, L. A. 2002. A detailed comparison of two transaction processing workloads. In WWC-5: IEEE 5th Annual Workshop on Workload Characterization.
30. ZHOU, J. AND ROSS, K. A. 2004. Buffering database operations for enhanced instruction cache performance. In SIGMOD '04: Proceedings of the 2004 ACM SIGMOD International Conference on Management of Data. ACM Press, New York, NY, 191-202.