Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2013, Pages

  Prasad, C ^a   Jiang, L ^a   Singh, D ^a   Agostinelli, M ^a   Auth, C ^a   Bai, P ^a   Eiles, T ^a   Hicks, J ^a   Jan, C H ^a   Mistry, K ^a   Natarajan, S ^a   Niu, B ^a   Packan, P ^a   Pantuso, D ^a   Post, I ^a   Ramey, S ^a   Schmitz, A ^a   Sell, B ^a   Suthram, S ^a   Thomas, J ^a   Tsai, C ^a   Vandervoorn, P ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL DATA; PROCESS TECHNOLOGIES; SELF-HEAT; THERMAL MODELING; TRIGATE;

RELIABILITY;

EID: 84880982248     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2013.6532036     Document Type: Conference Paper

References (11)

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11. D. A. Dallmann and K. Shenai, "Scaling Constraints Imposed by Self-Heating in Submicron SOI MOSFETs,", IEEE Trans. Elec. Dev., Vol. 42, pp. 489-496, 1995