Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2013, Pages

  Rahman, A ^a   Bai, P ^a   Curello, G ^a   Hicks, J ^a   Jan, C H ^a   Jamil, M ^a   Park, J ^a   Phoa, K ^a   Rahman, M S ^a   Tsai, C ^a   Woolery, B ^a   Yeh, J Y ^a  

^a INTEL CORPORATION   (United States)

Author keywords

breakdown; BTI; CMOS; High K dielectric; metal gate; Reliability; SILC; SoC; TDDB; tri gate

Indexed keywords

BREAKDOWN; BTI; HIGH-K DIELECTRIC; METAL GATE; SILC; SOC; TDDB; TRIGATE;

CMOS INTEGRATED CIRCUITS; OPTIMIZATION; RELIABILITY;

INTEGRATED CIRCUITS;

EID: 84880982809     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2013.6532105     Document Type: Conference Paper

References (12)

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12. S. Ramey et al., "Intrinsic Transistor Reliability Improvements from 22nm Tri-Gate Technology," to appear in IRPS Sym Proc., 2013.