A neuromorphic VLSI design for spike timing and rate based synaptic plasticity

Neural Networks

Volumn 45, Issue , 2013, Pages 70-82

  Rahimi Azghadi, Mostafa ^a   Al Sarawi, Said ^a   Abbott, Derek ^a   Iannella, Nicolangelo ^a  

^a UNIVERSITY OF ADELAIDE   (Australia)

Author keywords

BCM; Neuromorphic VLSI; Rate based plasticity; Spike timing dependent plasticity; Synaptic plasticity

Indexed keywords

BCM; BIOLOGICAL EXPERIMENTS; NEUROMORPHIC VLSI; SPIKE TIMING DEPENDENT PLASTICITIES; SYNAPTIC PLASTICITY; SYNAPTIC PLASTICITY RULES; VARIATION-AWARE DESIGN; VLSI IMPLEMENTATION;

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DESIGN; ELECTRIC NETWORK ANALYSIS; VLSI CIRCUITS;

TIMING CIRCUITS;

ARTICLE; CONTROLLED STUDY; LEARNING ALGORITHM; MATHEMATICAL COMPUTING; MATHEMATICAL MODEL; MONTE CARLO METHOD; NERVE CELL NETWORK; NERVE CELL PLASTICITY; NERVE CONDUCTION; PRIORITY JOURNAL; TRIPLET BASED SPIKE TIMING DEPENDENT PLASTICITY;

BCM; NEUROMORPHIC VLSI; RATE BASED PLASTICITY; SPIKE TIMING DEPENDENT PLASTICITY; SYNAPTIC PLASTICITY;

ACTION POTENTIALS; ANIMALS; ARTIFICIAL INTELLIGENCE; HUMANS; NEURONAL PLASTICITY; NEURONS; NUMERICAL ANALYSIS, COMPUTER-ASSISTED; SEMICONDUCTORS; SYNAPSES; TIME FACTORS;

EID: 84880835986     PISSN: 08936080     EISSN: 18792782     Source Type: Journal    
DOI: 10.1016/j.neunet.2013.03.003     Document Type: Article

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