A CMOS spiking neural network circuit with symmetric/asymmetric STDP function

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E92-A, Issue 7, 2009, Pages 1690-1698

  Tanaka, Hideki ^a   Morie, Takashi ^a   Aihara, Kazuyuki ^b,c  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^c JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

Associative memory; LSI implementation; Spike timing dependent synaptic plasticity (STDP); Spiking neuron model

Indexed keywords

ANALOG CIRCUITS; ASSOCIATIVE PROCESSING; ASSOCIATIVE STORAGE; ASYNCHRONOUS SEQUENTIAL LOGIC; CMOS INTEGRATED CIRCUITS; FIRING (OF MATERIALS); INTELLIGENT AGENTS; NEURAL NETWORKS; NEURONS;

ANALOG CMOS CIRCUIT; ASSOCIATIVE MEMORY; CMOS PROCESS TECHNOLOGY; LSI IMPLEMENTATION; SPIKE-TIMING-DEPENDENT SYNAPTIC PLASTICITIES; SPIKING NEURAL NETWORKS; SPIKING NEURON MODELS; SYMMETRIC FUNCTIONS;

TIMING CIRCUITS;

EID: 77955494138     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1587/transfun.E92.A.1690     Document Type: Article

References (14)

1. W. Maass, "Networks of spiking neurons: The third generation of neural network models," Trans. Soc. Comput. Simul. Int., vol.14, no.4, pp.1659-1671, 1997. (Pubitemid 28057273)
2. W. Maass and C.M. Bishop, eds., Pulsed neural networks, MIT Press, Cambridge, MA, USA, 1999.
3. S.J. Thorpe and J. Gautrais, "Rapid visual processing using spike asynchrony," NIPS, ed. M. Mozer, M.I. Jordan, and T. Petsche, pp.901-907, MIT Press, 1996.
4. K. Sasaki, T. Morie, and A. Iwata, "A VLSI spiking feedback neural network with negative thresholding and its application to associative memory," IEICE Trans. Electron., vol.E89-C, no.11, pp.1637-1644, Nov. 2006.
5. H. Tanaka, T. Morie, and K. Aihara, "Associative memory operation in a hopfield-type spiking neural network with modulation of resting membrane potential," Int. Symp. on Nonlinear Theory and its Applications (NOLTA 2005), pp.313-316, Oct. 2005.
6. G.Q. Bi and M.M. Poo, "Synaptic modifications in cultured hippocampal neurons: Dependence on spike timing, synaptic strength, and postsynaptic cell type," J. Neuroscience, vol.18, pp.10462-10472, 1993.
7. M. Nishiyama, K. Hong, K. Mikoshiba, M.M. Poo, and K. Kato, "Calcium stores regulate the polarity and input specificity of synaptic modification," Nature, vol.408, pp.584-588, 2000.
8. M. Tsukada, T. Aihara, Y. Kobayashi, and H. Shimazaki, "Spatial analysis of spike-timing-dependent ltp and ltd in the ca1 area of hippocampal slices using optical imaging," Hippocampus, vol.15, no.1, pp.104-109, 2005. (Pubitemid 40340246)
9. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI reconfigurable network of integrate-and-fire neurons with spike-based learning synapses," Proc. 12th European Symposium on Artificial Neural Networks (ESANN04), pp.405-410, 2004.
10. A. Bofill-i Petit and A. Murray, "Synchrony detection and amplification by silicon neurons with stdp synapses," IEEE Trans. Neural Netw., vol.15, no.5, pp.1296-1304, Sept. 2004.
11. H. Tanaka, T. Morie, and K. Aihara, "A CMOS synapse with STDP function and its application to hopfield-type associative memory," Int. Symp. on Nonlinear Theory and its Applications (NOLTA2006), pp.495-498, Sept. 2006.
12. H. Tanaka, T. Morie, and K. Aihara, "A CMOS circuit for STDP with a symmetric time window," Brain-Inspired IT III, International Congress Series, vol.1301, pp.152-155, Elsevier, July 2007.
13. H. Tanaka, T. Morie, and K. Aihara, "Evaluation of a CMOS spiking neural network circuit with STDP function," 15th IEEE Int. Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2007), pp.313-316, July 2007.
14. T. Morie, K. Murakoshi, M. Nagata, and A. Iwata, "Pulse modulation techniques for nonlinear dynamical systems and a CMOS chaos circuit with arbitrary 1-D maps," IEICE Trans. Electron., vol.E87-C, no.11, pp.1856-1862, Nov. 2004.