Resistive computing: Memristors-enabled signal multiplication

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 60, Issue 5, 2013, Pages 1241-1249

  Shin, Sangho ^a   Kim, Kyungmin ^a   Kang, Sung Mo ^a,b  

^a University of California Santa Cruz   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

memristive devices; Memristors; pattern matching; resistive computing; stateful logic; XNOR; XOR

Indexed keywords

COMPUTATION THEORY; COMPUTER CIRCUITS; PATTERN MATCHING;

COMPLEX INPUTS; CONDITIONAL SETS; LOGIC COMPUTATION; MEMRISTIVE DEVICES; MULTIPLIER CIRCUITS; RESISTIVE COMPUTING; STATEFUL LOGIC; XNOR;

MEMRISTORS;

EID: 84877752159     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2013.2244434     Document Type: Article

References (21)

1. ERD/ERM Final Rep., 2010, ITRS.
2. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, pp. 80-83, May 2008. (Pubitemid 351630336)
3. L. O. Chua and S. M. Kang, "Memristive devices and systems," Proc. IEEE, vol. 64, pp. 209-223, Feb. 1976.
4. M. Di Ventra, Y. V. Pershin, and L. O. Chua, "Circuit elements with memory: Memristors, memcapacitors, and meminductors," Proc. IEEE, vol. 97, no. 10, pp. 1717-1724, Oct. 2009.
5. D. B. Strukov and K. K. Likharev, "CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, pp. 888-900, 2005. (Pubitemid 40666599)
6. G. S. Snider and R. S. Williams, "Nano/CMOS architectures using a fieldprogrammable nanowire interconnect," Nanotechnology, vol. 18, no. 3, p. 035 204, Jan. 2007.
7. S. Shin, K. Kim, and S.-M. Kang, "Memristor applications for programmable analog ICs," IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 266-274, Mar. 2011.
8. B. Mouttet, "Proposal for memristors in signal processing," in Proc. Nano-Net 2008, 2009, pp. 11-13.
9. S. H. Jo,T.Chang, I.Ebong, B.B. Bhadviya, P.Mazumder, and W. Lu, "Nanoscale memristor device as synapse in neuromorphic systems," Nano Lett., vol. 10, no. 4, pp. 1297-1301, Mar. 2010.
10. D. B. Strukov and R. S.Williams, "Four-dimensional address topology for circuits with stacked multilayer crossbar arrays," Proc. Natl. Acad. Sci., vol. 106, no. 48, pp. 20155-20158, Dec. 1, 2009.
11. P. J. Kuekes, D. R. Stewart, and R. S. Williams, "The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits," J. Appl. Phys., vol. 97, p. 034301, 2005.
12. J. Borghetti, Z. Li, J. Straznicky, X. Li, D. A. Ohlberg, W. Wu, D. R. Stewart, and R. S.Williams, "A hybrid nanomemristor/transistor logic circuit capable of self-programming," Proc. Natl. Acad. Sci., vol. 106, no. 6, pp. 1699-1703, Feb. 2009.
13. J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, "'Memristive' switches enable 'stateful' logic operations via material implication," Nature, vol. 464, pp. 873-875, Apr. 2010.
14. K. Kim, S. Shin, and S.-M. Kang, "Stateful logic pipeline architecture," in Proc. ISCAS, May 2011, pp. 2497-2500.
15. S. Shin, K. Kim, and S.-M. Kang, "Reconfigurable stateful NOR gate for large-scale logic-array integrations," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 7, pp. 442-446, Jul. 2011.
16. K. Kim, S. Shin, and S. M. Kang, "Field programmable stateful logic array," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 12, pp. 1800-1813, Dec. 2011.
17. S. Shin, K. Kim, and S. M. Kang, "Memristive XOR for resistive multiplier," Electron. Lett., vol. 48, no. 2, pp. 78-80, Jan. 2012.
18. S. Shin, K. Kim, and S.-M. Kang, "Memristive computing- multiplication and correlation," in Proc. ISCAS, May 2012, pp. 1608-1611.
19. L. O. Chua, "Memristor-The missing circuit element," IEEE Trans. Circuit Theory, vol. CT-18, no. 5, pp. 507-519, Sep. 1971.
20. G. Gill, J. Hansen, andM. Singh, "Loop pipelining for high-throughput stream computation using self-timed rings," in Proc. ICCAD, Nov. 2006, pp. 289-296.
21. J. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufmann, 1996.