Reconfigurable stateful nor gate for large-scale logic-array integrations

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 58, Issue 7, 2011, Pages 442-446

  Shin, Sangho ^a   Kim, Kyosun ^b   Kang, Sung Mo ^a  

^a University of California Santa Cruz   (United States)

^b SolarLight Ltd   (South Korea)

Author keywords

Material implication; memristive device; pipeline architecture; stateful logic

Indexed keywords

MEMRISTORS; NANOWIRES; PIPELINES;

FIELD PROGRAMMABLES; INTERCONNECT FABRICS; LOGIC STRUCTURES; MEMRISTIVE DEVICE; NANOWIRE CROSSBARS; PIPELINE ARCHITECTURE; RECONFIGURABLE; STATEFUL LOGIC;

RECONFIGURABLE HARDWARE;

EID: 79960739050     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2011.2158253     Document Type: Article

References (7)

1. L. O. Chua and S. M. Kang, "Memristive devices and systems," Proc. IEEE, vol. 64, no. 2, pp. 209-223, Feb. 1976.
2. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S.Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp. 80-83, May 2008. (Pubitemid 351630336)
3. J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, "'Memristive' switches enable 'stateful' logic operations via material implication," Nature, vol. 464, no. 7290, pp. 873-876, Apr. 2010.
4. G. S. Snider and R. S. Williams, "Nano/CMOS architectures using a fieldprogrammable nanowire interconnect," Nanotechnology, vol. 18, no. 3, p. 035 204, Jan. 2007.
5. P. J. Kuekes, D. R. Stewart, and R. S. Williams, "The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits," J. Appl. Phys., vol. 97, no. 3, pp. 0343011-0343015, Feb. 2005.
6. D. B. Strukov and K. K. Likharev, "CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, no. 6, pp. 888-901, Jun. 2005.
7. K. Kim, S. Shin, and S.-M. Kang, "Stateful logic pipeline architecture," in Proc. IEEE Int. Conf. Circuits Syst., May 2011, pp. 2497-2500.