PATUS for convenient high-performance stencils: Evaluation in earthquake simulations

International Conference for High Performance Computing, Networking, Storage and Analysis, SC

Volumn , Issue , 2012, Pages

  Christen, Matthias ^a   Schenk, Olaf ^a   Cui, Yifeng ^b  

^a UNIVERSITY OF LUGANO   (Switzerland)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX SIMULATION; DISCRETIZATIONS; EARTHQUAKE SIMULATION; MANY-CORE PROCESSORS; PARALLEL EFFICIENCY; PROGRAMMER PRODUCTIVITY; SEISMIC APPLICATION; STENCIL COMPUTATIONS;

EARTHQUAKES; NETWORK COMPONENTS; PRODUCTIVITY; SPECIFICATION LANGUAGES;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 84877717516     PISSN: 21674329     EISSN: 21674337     Source Type: Conference Proceeding    
DOI: 10.1109/SC.2012.95     Document Type: Conference Paper

References (28)

1. Y. Cui, K. Olsen, T. Jordan, K. Lee, J. Zhou, P. Small, D. Roten, G. Ely, D. Panda, A. Chourasia, J. Levesque, S. Day, and P. Maechling, "Scalable Earthquake Simulation on Petascale Supercomputers," in Proc. ACM/IEEE Int'l Conference for High Performance Computing, Networking, Storage and Analysis (SC 2010), 2010, pp. 1-20.
2. M. Christen, O. Schenk, and H. Burkhart, "PATUS: A Code Generation and Autotuning Framework For Parallel Iterative Stencil Computations on Modern Microarchitectures," in Proc. IEEE Int'l Parallel & Distributed Processing Symposium (IPDPS 2011), 2011, pp. 1-12.
3. M. Christen, "Generating and Auto-Tuning Parallel Stencil Codes," Ph.D. dissertation, University of Basel, Switzerland, 2011.
4. K. Olsen, "Simulation of Three-Dimensional Wave Propagation in the Salt Lake Basin," Ph.D. dissertation, Univ. of Utah, 1994.
5. C. Marcinkovich and K. Olsen, "On the Implementation of Perfectly Matched Layers in a 3D Fourth-Order Velocity-Stress Finite-Difference Scheme," J. Geophys. Res., vol. 108 (B5), 2003.
6. M. Christen, O. Schenk, E. Neufeld, P. Messmer, and H. Burkhart, "Parallel Data-Locality Aware Stencil Computations on Modern Micro-Architectures," in Proc. IEEE Int'l Parallel & Distributed Processing Symposium (IPDPS 2009), May 2009, pp. 1-10.
7. M. Frigo and V. Strumpen, "The Cache Complexity of Multithreaded Cache Oblivious Algorithms," in Proc. ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2006), 2006, pp. 271-280.
8. R. Strzodka, M. Shaheen, D. Pajak, and H. Seidel, "Cache oblivious parallelograms in iterative stencil computations," in Proc. ACM Int'l Conference on Supercomputing (ICS 2010), 2010, pp. 49-59.
9. Y. Tang, R. Chowdhury, B. Kuszmaul, C. Luk, and C. Leiserson, "The Pochoir Stencil Compiler," in Proc. ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2011), 2011, pp. 117-128.
10. J. Treibig, G. Wellein, and G. Hager, "Efficient Multicore-Aware Parallelization Strategies for Iterative Stencil Computations," J. Comp. Sci., vol. 2, no. 2, pp. 130-137, 2011.
11. D. Wonnacott, "Time skewing for parallel computers," in Proc. Int'l Workshop on Compilers for Parallel Computing (CPC 1999). Springer-Verlag, 1999, pp. 477-480.
12. D. Unat, X. Cai, and S. Baden, "Mint: Realizing CUDA Performance in 3D Stencil Methods with Annotated C," in Proc. ACM Int'l Conference on Supercomputing (ICS 2011), 2011, pp. 214-224.
13. N. Maruyama, T. Nomura, K. Sato, and S. Matsuoka, "Physis: An Implicitly Parallel Programming Model for Stencil Computations on Large-Scale GPU-Accelerated Supercomputers," in Proc. ACM/IEEE Int'l Conference for High Performance Computing, Networking, Storage and Analysis (SC 2011). IEEE Computer Society, 2011.
14. J. Meng and K. Skadron, "A Performance Study for Iterative Stencil Loops on GPUs with Ghost Zone Optimizations," Int. J. Parallel Prog., vol. 39, pp. 115-142, February 2011.
15. Y. Yang, H. Cui, X. Feng, and J. Xue, "A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs," J. Comp. Sci. Tech., vol. 27, pp. 57-74, 2012.
16. Z. Li and Y. Song, "Automatic Tiling of Iterative Stencil Loops," ACM Trans. Program. Lang. Syst., vol. 26, no. 6, pp. 975-1028, 2004. (Pubitemid 41270296)
17. K. Datta, "Auto-tuning Stencil Codes for Cache-Based Multicore Platforms," Ph.D. dissertation, Univ. of California, Berkeley, 2009.
18. S. Kamil, C. Chan, L. Oliker, J. Shalf, and S. Williams, "An Auto-tuning Framework For Parallel Multicore Stencil Computations," in Proc. IEEE Int'l Parallel & Distributed Processing Symposium (IPDPS 2010), April 2010.
19. A. Nguyen, N. Satish, J. Chhugani, C. Kim, and P. Dubey, "3.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs," in Proc. ACM/IEEE Int'l Conference for High Performance Computing, Networking, Storage and Analysis (SC 2010). IEEE Computer Society, 2010.
20. T. Malas, A. Ahmadia, J. Brown, J. Gunnels, and D. Keyes, "Optimizing the Performance of Streaming Numerical Kernels on the IBM Blue Gene/P PowerPC 450 Processor," IJHPCA, 2012.
21. L. Renganarayanan, D. Kim, S. Rajopadhye, and M. Strout, "Parameterized Tiled Loops for Free," in Proc. ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2007), 2007, pp. 405-414.
22. U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, "A Practical Automatic Polyhedral Parallelizer and Locality Optimizer," in Proc. ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2008), 2008.
23. M. Hall, J. Chame, C. Chen, J. Shin, G. Rudy, and M. Khan, "Loop Transformation Recipes for Code Generation and Auto-Tuning," in Languages and Compilers for Parallel Computing, ser. Lecture Notes in Computer Science, G. Gao, L. Pollock, J. Cavazos, and X. Li, Eds., vol. 5898. Springer Berlin / Heidelberg, 2010, pp. 50-64.
24. K. Brown, A. Sujeeth, H. Lee, T. Rompf, H. Chafi, M. Odersky, and K. Olukotun, "A Heterogeneous Parallel Framework for Domain-Specific Languages," in Proc. Int'l Conference on Parallel Architectures and Compilation Techniques (PACT 2011), 2011, pp. 89-100.
25. H. Bae, L. Bachega, C. Dave, S. Lee, S. Lee, S. Min, R. Eigenmann, and S. Midkiff, "Cetus: A Source-to-Source Compiler Infrastructure for Multicores," in Proc. Int'l Workshop on Compilers for Parallel Computing (CPC 2009), 2009.
26. H. Mössenböck, M. Löberbauer, and A. Wöß, "The Compiler Generator Coco/R," http://www.ssw.uni-linz.ac.at/coco, accessed April 2012.
27. J. McCalpin and D. Wonnacott, "Time skewing: A value-based approach to optimizing for memory locality," Department of Computer Science, Rutgers University, Tech. Rep. DCS-TR-379, 1998.
28. J. Treibig, G. Hager, and G. Wellein, "LIKWID: A Lightweight Performance-oriented Tool Suite for x86 Multicore Environments," in Proc. First International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI2010), San Diego CA, 2010.