5-D blocking optimization for stencil computations on modern CPUs and GPUs

2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2010

Volumn , Issue , 2010, Pages

  Nguyen, Anthony ^a   Satish, Nadathur ^a   Chhugani, Jatin ^a   Kim, Changkyu ^a   Dubey, Pradeep ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCKING ALGORITHMS; DATA-LEVEL PARALLELISM; LARGE CLASS; LATTICE BOLTZMANN METHOD; MEMORY BANDWIDTHS; MULTIPLE TIME STEP; NEAREST-NEIGHBORS; ON CHIP MEMORY; PRECISION FLOATING POINT; SPATIAL GRIDS; STENCIL COMPUTATIONS; TEMPORAL BLOCKING;

ALGORITHMS; BANDWIDTH;

PROGRAM PROCESSORS;

EID: 78650806116     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SC.2010.2     Document Type: Conference Paper

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