PATUS: A code generation and autotuning framework for parallel iterative stencil computations on modern microarchitectures

Proceedings - 25th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2011

Volumn , Issue , 2011, Pages 676-687

  Christen, Matthias ^a   Schenk, Olaf ^a   Burkhart, Helmar ^a  

^a UNIVERSITY OF BASEL   (Switzerland)

Author keywords

autotuning; code generation; high performance computing; stencil computations

Indexed keywords

AUTOTUNING; CODE GENERATION; COMPLEX HARDWARE; GRAPHICS PROCESSING UNIT; HARDWARE ARCHITECTURE; HIGH PERFORMANCE COMPUTING; IMAGE PROCESSING APPLICATIONS; MANY CORE; MICRO ARCHITECTURES; MULTI CORE; MULTIGRID METHODS; OPTIMIZATION STRATEGY; PARALLEL IMPLEMENTATIONS; PARALLELIZATIONS; PDE SOLVERS; SCIENTIFIC COMPUTING APPLICATIONS; STENCIL COMPUTATIONS; TIME-TO-SOLUTION;

ARCHITECTURE; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE SELECTION AND EVALUATION; DISTRIBUTED PARAMETER NETWORKS; IMAGE PROCESSING; OPTIMIZATION; PROGRAM PROCESSORS;

NETWORK COMPONENTS;

EID: 80053238973     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2011.70     Document Type: Conference Paper

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