LIKWID: A lightweight performance-oriented tool suite for x86 multicore environments

Proceedings of the International Conference on Parallel Processing Workshops

Volumn , Issue , 2010, Pages 207-216

  Treibig, Jan ^a   Hager, Georg ^a   Wellein, Gerhard ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE COUNTERS; KEY PROBLEMS; MEASURING PERFORMANCE; MICRO ARCHITECTURES; MULTICORE CHIPS; MULTICORE ENVIRONMENTS; SHARED CACHE; SHARED MEMORIES; TOOLSUITE; USER CODES;

APPLICATION PROGRAMMING INTERFACES (API); TOPOLOGY;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 78649844813     PISSN: 15302016     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPPW.2010.38     Document Type: Conference Paper

References (9)

1. G. Jost, J. Haoqiang, J. Labarta, J. Gimenez, J. Caubet: Performance analysis of multilevel parallel applications on shared memory architectures. Proceedings of the Parallel and Distributed Processing Symposium, 2003.
2. M. Gerndt, E. Kereku: Automatic Memory Access Analysis with Periscope. ICCS '07: Proceedings of the 7th international conference on Computational Science, 2007, 847-854.
3. M. Gerndt, K. Fürlinger, E. Kereku: Periscope: Advanced Techniques for Performance Analysis. PARCO, 2005, 15-26.
4. D. Terpstra, H. Jagode, H. You, J. Dongarra: Collecting Performance Data with PAPI-C. Proceedings of the 3rd Parallel Tools Workshop, Springer Verlag, Dresden, Germany, 2010.
5. S. Browne, C. Deane, G. Ho, P. Mucci: PAPI: A Portable Interface to Hardware Performance Counters. Proceedings of Department of Defense HPCMP Users Group Conference, June 1999.
6. Paul J. Drongowski: Basic Performance Measurements for AMD Athlon 64, AMD Opteron and AMD Phenom Processors. Technical Note, Advanced Micro Devices, Inc. Boston Design Center, September 2008.
7. L. DeRose, B. Homer, and D. Johnson: Detecting application load imbalance on high end massively parallel systems. Euro- Par 2007 Parallel Processing Conference, 2007, 150-159.
8. J. Treibig, G. Wellein, G. Hager: Efficient multicore-aware parallelization strategies for iterative stencil computations. Submitted to Journal of Computational Science, 2010. Preprint http://arxiv.org/abs/1004.1741.
9. M. Wittmann, G. Hager and G. Wellein. Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory. Workshop on Large-Scale Parallel Processing 2010 (IPDPS2010), Atlanta, GA, April 23, 2010. Preprint http://arxiv.org/abs/0912.4506