Exploring and exploiting the multilevel parallelism inside ssds for improved performance and endurance

IEEE Transactions on Computers

Volumn 62, Issue 6, 2013, Pages 1141-1155

  Hu, Yang ^a   Jiang, Hong ^b   Feng, Dan ^a   Tian, Lei ^b   Luo, Hao ^b   Ren, Chao ^a  

^a HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

^b UNIVERSITY OF NEBRASKA LINCOLN   (United States)

Author keywords

advanced commands; allocation schemes; endurance; internal parallelism; NAND Flash based SSD; performance

Indexed keywords

ADVANCED COMMANDS; ALLOCATION SCHEMES; INTERNAL PARALLELISM; NAND FLASH-BASED SSD; PERFORMANCE;

COMPUTER SCIENCE; DURABILITY; SOFTWARE ENGINEERING;

FLASH-BASED SSDS;

EID: 84877299521     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.60     Document Type: Article

References (50)

1. A.R. Olson and D.J. Langlois, "Solid State Drives Data Reliability and Lifetime," White Paper. Imation Corp. http://www.imation. com/PageFiles/1189/SSD-Gov-DataReliability-WP.pdf, 2008.
2. W. Hutsell, J. Bowen, and N. Ekker, "Flash Solid State Disk Reliability," White Paper, Texas Memory Systems, http://www.ram san .com/files/f000252.pdf, 2008.
3. M-System, "Two Technologies Compared: NOR vs NAND," In White Paper, http://maltiel-consulting.com/Nonvolatile-Memory-NOR-vs-NAND.pdf, 2003.
4. "SLV vs. MLC: An Analysis of Flash Memory,"In White Paper, Super Talent Technology, Inc., http://www.supertalent.com/datasheets/SLC-vs- MLC%20whitepaper.pdf, 2013.
5. J. Cooke, "Introduction to Flash Memory (T1A)," Slides. http://www.slideshare.net/Flashdomain/introduction-to-flashmemory-t1a, 2008.
6. K.M. Greenan, D.D.E. Long, E.L. Miller, T. Schwarz, and A. Wildani, "Building Flexible, Fault-Tolerant Flash-Based Storage Systems," Proc. Fifth Workshop Hot Topics in System Dependability (HotDep '09), June 2009.
7. M. Moshayedi and P. Wilkison, "Enterprise SSDs," ACM Queue, vol. 6, pp. 32-39, July/Aug. 2008.
8. C. Dirik and B. Jacob, "The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth, Concurrency, Device Architecture, and System Organization," Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA '09), June 2009.
9. A.M. Caulfield, J. Coburn, T.I. Mollov, A. De, A. Akel, J. He, A. Jagatheesan, R.K. Gupta, A. Snavely, and S. Swanson, "Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing," Proc. ACM/IEEE Int'l Conf. for High Performance Computing, Networking, Storage and Analysis (SC '10), Nov. 2010.
10. A. Leventhal, "Flash Storage Today," ACM Queue, vol. 6, pp. 24-30, July/Aug. 2008.
11. G. Graefe, "The Five-Minute Rule Twenty Years Later, and How Flash Memory Changes the Rules," Proc. Third Int'l Workshop Data Management on New Hardware (DaMoN '07), June 2007.
12. A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: A Flash Translation Layer Employing Demand-Based Selective of Page-Level Address Mapping," Proc. ACM Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '09), Mar. 2009.
13. Y. Hu, H. Jiang, D. Feng, L. Tian, S. Zhang, J. Liu, W. Tong, Y. Qin, and L. Wang, "Achieving Page-Mapping FTL Performance at Block-Mapping FTL Cost by Hiding Address Translation," Proc. IEEE 26th Symp. Mass Storage Systems and Technologies (MSST '10), May 2010.
14. J. Shin, Z. Xia, N. Xu, R. Gao, X. Cai, S. Maeng, and E. Hsu, "FTL Design Exploration in Reconfigurable High-Performance SSD for Server Applications," Proc. 23rd Int'l Conf. Supercomputing (ICS '09), June 2009.
15. S. Lee, D. Park, T. Chung, D. Lee, S. Park, and H. Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation," ACM Trans. Embedded Computing Systems, vol. 6, no. 3, article 18, July 2007.
16. H. Kim and S. Ahn, "BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage," Proc. Sixth USENIX Conf. File and Storage Technologies (FAST '08), Feb. 2008.
17. J. Seol, H. Shim, J. Kim, and S. Maeng, "A Buffer Replacement Algorithm Exploiting Multi-Chip Parallelism in Solid State Disks," Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems (CASES '09), Oct. 2009.
18. S. Park, D. Jung, J. Kang, J. Kim, and J. Lee, "CFLRU: A Replacement Algorithm for Flash Memory," Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems (CASES '06), Oct. 2006.
19. H. Jo, J. Kang, S. Park, J. Kim, and J. Lee, "FAB: Flash-Aware Buffer Management Policy for Portable Media Players" IEEE Trans. Consumer Electronics, vol. 52, no. 2, pp. 485-493, May 2006. (Pubitemid 44203122)
20. F. Chen, D.A. Koufaty, and X. Zhang, "Understanding Intrinsic Characteristics and System Implications of Flash Memory Based Solid State Drives," Proc. 11th Int'l Joint Conf. Measurement and Modeling of Computer Systems (SIGMETRICS/Performance '09), June 2009.
21. L.M. Grupp, A.M. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P.H. Siegel, and J.K. Wolf, "Characterizing Flash Memory: Anomalies, Observations, and Applications," Proc. IEEE/ACM 42nd Ann. Int'l Symp. Microarchitecture (MICRO '09), Dec. 2009.
22. S. Boboila and P. Desnoyers, "Write Endurance in Flash Drives: Measurements and Analysis," Proc. Eighth USENIX Conf. File and Storage Technologies (FAST '10), Feb. 2010.
23. P. Desnoyers, "Empirical Evaluation of NAND Flash Memory Performance," Proc. SOSP Workshop Hot Topics in Storage and File Systems (HotStorage '09), Oct. 2009.
24. N. Agrawal, V. Prabhakaran, T. Wobber, J.D. Davis, M. Manasse, and R. Panigrahy, "Design Tradeoffs for SSD Performance," Proc. Usenix Ann. Technical Conf. (USENIX '08), June 2008.
25. J. Kang, J. Kim, C. Park, H. Park, and J. Lee, "A Multi-Channel Architecture for High-Performance and Flash-Based Storage System," J. Systems Architecture, vol. 53, pp. 644-658, 2007. (Pubitemid 46754996)
26. S. Park, E. Seo, J. Shin, S. Maeng, and J. Lee, "Exploiting Internal Parallelism of Flash-Based SSDs," IEEE Computer Architecture Letters, vol. 9, no. 1, pp. 9-12, Feb. 2010.
27. S. Park, S. Ha, K. Bang, and E. Chuang, "Design and Analysis of Flash Translation Layers for Multi-Channel NAND Flash Based Storage Devices," IEEE Trans. Consumer Electronics, vol. 55, no. 3, pp. 1392-1400, Aug. 2009.
28. K9XXG08UXA datasheet. http://www.samsung.com/products/semiconductor/ flash/technicallinfo/datasheets.htm, 2013.
29. K9NCG08U5M datasheet. http://www.samsung.com/products/semiconductor/ flash/technicallinfo/datasheets.htm, 2013.
30. Micro MT29F16G08FAA NAND Flash Memory Datasheet. http://www.micron.com// document-download/?documentId=4308, 2013.
31. Micro MT29F256G08CUCBB NAND Flash Memory Datasheet, http://www.micron. com//document-download/?documentId = 4368, 2013.
32. Intel JS29F64G08CAMD1 MD332 NAND Flash Memory datasheet. http://www.intel.com/design, 2013.
33. Toshiba TH58TVG7S2F NAND Flash Memory datasheet, http://www.toshiba.com/, 2013.
34. Hynix H27UCG8U5(D)A Series 64Gb NAND Flash datasheet, http://www.hynix.com/datasheet/, 2013.
35. Microsoft Enterprise Traces. http://iotta.snia.org/traces/list/BlockIO, 2013.
36. Application Note for nand Flash Memory (revision 2.0) http://www.samsung.com/glo bal/business/semiconductor/products/flash/downloads/ applicationnote/app-nand.pdf, 2013.
37. "Open NAND Flash Interface Specification,"revision2.2. http://onfi.org/wp-content/uploads/2009/02/ONFI%202-2% 20Gold.pdf, 2013.
38. "NAND Flash Performance Improvement Using Internal Data Move,"Technical Note TN-29-15, http://download.micron.com/pdf/tech-notes/ nand/tn2915.pdf, 2013.
39. "Using COPYBACK Operations to Maintain Data Integrity in NAND Devices,"Technical Note TN-29-41, http://www.eetasia. com/STATIC/PDF/ 200903/EEOL-2009MAR02-STOR-AN-01.pdf?SOURCES = DOWNLOAD, 2013.
40. "SSD Extension for DiskSim Simulation Environment," http://research.micro soft.com/en-us/downloads/b41019e2-1d2b-44d8-b512- ba35ab814cd4, 2013.
41. Y. Kim, B. Tauras, A. Gupta, D.M. Nistor, and B. Urgaonkar, "FlashSim: A Simulator for NAND Flash-Based Solid-State Drives," Technical Report CSE-09-008, Dept. of Computer Science and Eng., The Pennsylvania State Univ., PA, 2009.
42. J. Bucy, J. Schindler, S.W. Schlosser, and G.R. Ganger, "The DiskSim Simulation Environment Version 4.0 Reference Manual," Mellon Univ., Parallel Data Lab Technical Report CMU-PDL-08-101, May 2008.
43. E. Fal and S. Toledo, "Algorithms and Data Structures for Flash Memories," ACM Computing Surveys, vol. 37, no. 2, pp. 138-163, June 2005. (Pubitemid 41527575)
44. T. Chung, D. Park, S. Park, D. Lee, S. Lee, and H. Song, "System Software for Flash Memory: A Survey," Proc. Int'l Conf. Embedded and Ubiquitous Computing (EUC '06), pp. 394-404, 2006. (Pubitemid 44165938)
45. "UMass Trace Repository," http://traces.cs.umass.edu, 2013.
46. "Weal-Leveling Techniques in NAND Flash Devices," Technical Note TN-29-42. http://download.micron.com/pdf/technotes/nand/tn2942-nand-wear- leveling.pdf, 2013.
47. Y. Hu, H. Jiang, D. Feng, L. Tian, H. Luo, and S. Zhang, "Performance Impact and Interplay of SSD Parallelism through Advanced Commands, Allocation Strategy and Data Granularity," Proc. Int'l Conf. Supercomputing (ICS '11), May/June 2011.
48. F. Chen, R. Lee, and X. Zhang, "Essential Roles of Exploiting Internal Parallelism of Flash Memory Based Solid State Drives in High-Speed Data Processing," Proc. IEEE Seventh Int'l Conf. High Performance Computer Architecture (HPCA '11), Feb. 2011.
49. C. Park, P. Talawar, D. Won, M. Jung, J. Im, S. Kim, and Y. Choi, "A High Performance Controller for NAND Flash-Based Solid State Disk," Proc. IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW '06), Feb. 2006.
50. L. Bouganim, B. Jonsson, and P. Bonnet, "uFLIP: Understanding Flash IO Patterns," Proc. Fourth Biennial Conf. Innovative Data Systems Research (CIDR '09), Jan. 2009.