Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation

2010 IEEE 26th Symposium on Mass Storage Systems and Technologies, MSST2010

Volumn , Issue , 2010, Pages

  Hu, Yang ^a   Jiang, Hong ^b   Feng, Dan ^a   Tian, Lei ^a,b   Zhang, Shuping ^c   Liu, Jingning ^a   Tong, Wei ^a   Qin, Yi ^a   Wang, Liuzheng ^a,b,c  

^a HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

^b UNIVERSITY OF NEBRASKA LINCOLN   (United States)

^c First Academy of CASIC   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED COMPUTER SYSTEMS; DYNAMIC RANDOM ACCESS STORAGE; FLASH MEMORY; PHYSICAL ADDRESSES; STATIC RANDOM ACCESS STORAGE;

ADDRESS TRANSLATION; ARRIVAL INTERVALS; FLASH TRANSLATION LAYER; PERFORMANCE ISSUES; PHYSICAL CHARACTERISTICS; SOLID STATE MEMORY; TRACE DRIVEN SIMULATION; WORKLOAD CHARACTERISTICS;

MAPPING;

EID: 77957832934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MSST.2010.5496970     Document Type: Conference Paper

References (31)

1. An Introduction to NAND Flash and How to Design It In to Your Next Product. http://download.micron.com/pdf/technotes/nand/tn2919.pdf
2. Eran Fal and Sivan Toledo. Algorithms and Data Structures for Flash Memories. In ACM Computing Surveys, Volume 37, June 2005.
3. Tae-Sun Chung, Dong-Joo Park, Sangwon Park, Dong-Ho Lee, Sang-Won Lee and Ha-Joo Song. System Software for Flash Memory: A Survey. In Proc. of EUC'06, Auguest 2006.
4. Sang-Won LEE, Dong-Joo Park, Tae-Sun Chung, Dong-Ho LEE, Sang-Won Park and Ha-Joo Song. A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation. In ACM Transactions on Embedded Computing Systems, Volume 6, July 2007.
5. Sungjin Lee, Dongkun Shin, Young-Jin Kim and Jihong Kim. LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems. In Proc. of SPEED'08, February 2008.
6. Jeong-Uk Kang, Heeseung Jo, Jin-Soo Kim and Joonwon Lee. A Superblock-Based Flash Translation Layer for NAND Flash Memory. In Proc. of EMSOFT'06, October 2006.
7. Aayush Gupta, Youngjae Kim Bhuvan Urgaonkar. DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-Level Address Mapping. In Proc. of ASPLOS'09, March 2009.
8. M-System. Two Technologies Compared: NOR vs NAND. In White Paper, 2003.
9. K9XXG08UXA datasheet. http://www.samsung.Com/products/semicondutor/flash/ technicallinfo/datasheets.htm.
10. Jesung Kim, Jong Min Kim, Sam H.Noh, Sang Lyul Min and Yookun Cho. A Space-Efficient Flash Translation Layer for Compact Flash Systems. In IEEE Transactions on Consumer Electronics, Volume 48, May 2002.
11. UMass Trace Repository.http://traces.cs.umass.edu
12. The Openmail Trace. http://tesla.hpl.hp.com/opensource/openmail/.
13. Numonyx Phase Change Memory (P8P) 128-Mbit Parallel Phase Change Memory. http://www.numo nyx.com.
14. The Basics of Phase Change Memory (PCM) Technology. White Paper. http://www.numonyx.com.
15. S. Raoux, G. W. Burr, M. J. Breitwisch, C.T. Rettner, Y.-C. Chen, R. M. Shelby, M.Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, C. H. Lam. Phase-Change Random Access Memory: A Scalable Technology. In IBM Journal of Research and Development, 2008.
16. Cho. Beak-hyung, Lee. Kwang-jin, Park. Mu-hui. Phase Change Random Access Memory Device. United states patent 7639558. December 2009.
17. Jin Kyu Kim, Hyung Gyu Lee, Shinho Choi and Kyoung II Bahng. A PRAM and NAND Flash Hybrid Architecture for High-Performance Embedded Storage Subsystems. In Proc. of EMSOFT'08, October 2008.
18. Jin Hyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong, Hongseok Kim, Bryan S. Kim, Sang Lyul Min and Yookun Cho. Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture. In IEEE computer architecture letters, Volume 7, January-June 2008.
19. Guangyu Sun, Yongsoo Joo, Yibo Chen, Yiran Chen and Hai Li. A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement. In Proc. of HPCA'10, January 2010.
20. Youngwoo Park, Seung-Ho Lim, Chul Lee and Kyu Ho Park. PFFS: A Scalable Flash Memory File System for the Hybrid Architecture of Phase-change RAM and NAND Flash. In Proc. of SAC'08, March 2008.
21. Open NAND Flash Interface SpecificaRion. revision2.2. http://onfi.org/wp-content/uploads/2009/02/ONFI%202-%20Gold.pdf
22. Synchronous DRAM MT48LC64M4A2. http://www.micron.com.
23. Chanik park, Wonmoon Cheon, Jeonguk Kang, Kangho Roh and Wonhee Cho. A Reconfigurable FTL Architecture for NAND Flash-Based Applications. In ACM Transaction Embedded Computing Systems, Volume 7, July 2008.
24. Nitin Agrawal, Vijiayan Prabhakaran, Ted Wobber. Design Tradeoffs for SSD Performance. In Proc. of USENIX'08, June 2008.
25. Ji-Yong Shin, Zeng-Lin Xia, Ning-Yi Xu, Rui Gao, Xiong-Fei Cai, Seungryoul Maeng and eng-Hsiung Hsu. FTL Design Exploration in Reconfigurable High-Performance SSD for Server Applications. In Proc. of ISC'09, June 2009.
26. Hyojun Kim and Seongjun Ahn. BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage. In Proc. of FAST'08, February 2008.
27. Feng Chen, David A. Koufaty and Xiaodong Zh- ang. Understanding Intrinsic Characteristics and System Implications of Flash Memory based Solid State Drives. In Proc. of SIGMETRICS' 09, February 2009.
28. Abhishek Rajimwale, Vijayan Prabhakaran, John D. Davis. Block Management in Solid-State Devices. In Proc. of USENIX' 09, June 2009.
29. Simona Boboila and Peter Desnoyers. Write Endurance in Flash Drives: Measurements and Analysis. In Proc. of FAST'10, February 2010.
30. Li-Pin Chang and Tei-Wei Kuo. Efficient Manangement for Large-Scale Flash-Memory Storage Systems with Resource Conservation. In ACM Transactions on Storage, Volume 1, November 2005.
31. Luc Bouganim, Bjorn Por Jonsson and Philippe Bonnet. uFLIP: Understanding Flash IO Patterns. In Proc. of CIDR'09, January 2009.