DFTL: A flash translation layer employing demand-based caching of page-level address mappings

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2009, Pages 229-240

  Gupta, Aayush ^a   Kim, Youngjae ^a   Urgaonkar, Bhuvan ^a  

^a The Center for Nanotechnology Education and Utilization   (United States)

Author keywords

Flash Translation Layer; Management; Storage System

Indexed keywords

FLASH MEMORY; MANAGEMENT; PHYSICAL ADDRESSES; RESPONSE TIME (COMPUTER SYSTEMS); TRANSLATION (LANGUAGES); VIRTUAL ADDRESSES;

EXPERIMENTAL EVALUATION; FINANCIAL INSTITUTION; FLASH TRANSLATION LAYER; MECHANICAL MOVING PARTS; SIMULATION FRAMEWORK; STORAGE SYSTEMS; TECHNOLOGICAL ADVANCES; VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATIONS;

EMBEDDED SYSTEMS;

EID: 67650065541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508244.1508271     Document Type: Conference Paper

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