-
3
-
-
34547223922
-
-
M-System. In white paper
-
M-System. Two Technologies Compared: NOR vs NAND. In white paper, 2003. http://maltiel-consulting.com/Nonvolatile-Memory-NOR-vs-NAND.pdf
-
(2003)
Two Technologies Compared: NOR Vs NAND
-
-
-
4
-
-
79959585928
-
-
In white paper
-
SLV vs. MLC: An Analysis of Flash Memory. In white paper. Super Talent Technology, Inc. http://www.supertalent.com/datasheets/SLC-vs-MLC%20whitepaper. pdf
-
SLV Vs. MLC: An Analysis of Flash Memory
-
-
-
5
-
-
79959594060
-
Introduction to Flash Memory (T1A)
-
J. Cooke. Introduction to Flash Memory (T1A). Slides. 2008. http://www.slideshare.net/Flashdomain/introduction-to-flash-memory-t1a
-
(2008)
Slides
-
-
Cooke, J.1
-
6
-
-
77953990698
-
Building Flexible, Fault-Tolerant Flash-based Storage Systems
-
K. M. Greenan, D. D. E. Long, E. L. Miller, T. Schwarz and A. Wildani. Building Flexible, Fault-Tolerant Flash-based Storage Systems. In Proc. of HotDep'09, June 2009.
-
Proc. of HotDep'09, June 2009
-
-
Greenan, K.M.1
Long, D.D.E.2
Miller, E.L.3
Schwarz, T.4
Wildani, A.5
-
8
-
-
70450286395
-
The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth, Concurrency, Device Architecture, and System Organization
-
C. Dirik and B. Jacob. The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth, Concurrency, Device Architecture, and System Organization. In Proc. of ISCA'09, June 2009.
-
Proc. of ISCA'09, June 2009
-
-
Dirik, C.1
Jacob, B.2
-
9
-
-
78650839010
-
Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing
-
A. M. Caulfield, J. Coburn, T. I. Mollov, A. De, A. Akel, J. He, A. Jagatheesan, R. K. Gupta, A. Snavely and S. Swanson. Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing. In Proc. of SC'10, November 2010.
-
Proc. of SC'10, November 2010
-
-
Caulfield, A.M.1
Coburn, J.2
Mollov, T.I.3
De, A.4
Akel, A.5
He, J.6
Jagatheesan, A.7
Gupta, R.K.8
Snavely, A.9
Swanson, S.10
-
11
-
-
77952391462
-
The Five-minute Rule Twenty Years Later, and How Flash Memory Changes the Rules
-
G. Graefe. The Five-minute Rule Twenty Years Later, and How Flash Memory Changes the Rules. In Proc. of DaMoN'07. June 15, 2007
-
Proc. of DaMoN'07. June 15, 2007
-
-
Graefe, G.1
-
12
-
-
67650065541
-
DFTL: A Flash Translation Layer Employing Demand-based Selective of Page-level Address Mapping
-
A. Gupta, Y. Kim and B. Urgaonkar. DFTL: A Flash Translation Layer Employing Demand-based Selective of Page-level Address Mapping. In Proc. of ASPLOS'09. March 7-11, 2009.
-
Proc. of ASPLOS'09. March 7-11, 2009
-
-
Gupta, A.1
Kim, Y.2
Urgaonkar, B.3
-
13
-
-
77957832934
-
Achieving Page-Mapping FTL Performance at Block-Mapping FTL Cost by Hiding Address Translation
-
Y. Hu, H. Jiang, D. Feng, L. Tian, S. Zhang, J. Liu, W. Tong, Y. Qin and L. Wang. Achieving Page-Mapping FTL Performance at Block-Mapping FTL Cost by Hiding Address Translation. In Proc. of MSST'10. May 3-7, 2010.
-
Proc. of MSST'10. May 3-7, 2010
-
-
Hu, Y.1
Jiang, H.2
Feng, D.3
Tian, L.4
Zhang, S.5
Liu, J.6
Tong, W.7
Qin, Y.8
Wang, L.9
-
14
-
-
70449711367
-
FTL Design Exploration in Reconfigurable High-Performance SSD for Server Applications
-
J. Shin, Z. Xia, N. Xu, R. Gao, X. Cai, S. Maeng and E. Hsu. FTL Design Exploration in Reconfigurable High-Performance SSD for Server Applications. In Proc. of ICS'09, June 2009.
-
Proc. of ICS'09, June 2009
-
-
Shin, J.1
Xia, Z.2
Xu, N.3
Gao, R.4
Cai, X.5
Maeng, S.6
Hsu, E.7
-
15
-
-
85025155936
-
A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation
-
Article 18, July
-
S. Lee, D. Park, T. Chung, D. Lee, S. Park and H. Song. A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation. ACM Transactions on Embedded Computing Systems, Vol.6, No.3, Article 18, July 2007.
-
(2007)
ACM Transactions on Embedded Computing Systems
, vol.6
, Issue.3
-
-
Lee, S.1
Park, D.2
Chung, T.3
Lee, D.4
Park, S.5
Song, H.6
-
16
-
-
85075012374
-
BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage
-
H. Kim and S. Ahn. BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage. In Proc. of FAST'08. February 26-29, 2008.
-
Proc. of FAST'08. February 26-29, 2008
-
-
Kim, H.1
Ahn, S.2
-
18
-
-
34547194263
-
CFLRU: A Replacement Algorithm for Flash Memory
-
S. Park, D. Jung, J. Kang, J. Kim and J. Lee. CFLRU: A Replacement Algorithm for Flash Memory. In Proc. of CASES'06, October 2006.
-
Proc. of CASES'06, October 2006
-
-
Park, S.1
Jung, D.2
Kang, J.3
Kim, J.4
Lee, J.5
-
19
-
-
33747027155
-
FAB: Flash-Aware Buffer Management Policy for Portable Media Players
-
M ay
-
H. Jo, J. Kang, S Park, J. Kim and J. Lee. FAB: Flash-Aware Buffer Management Policy for Portable Media Players. IEEE Transaction on Consumer Electronics, Vol.52, No.2, M ay 2006.
-
(2006)
IEEE Transaction on Consumer Electronics
, vol.52
, Issue.2
-
-
Jo, H.1
Kang, J.2
Park, S.3
Kim, J.4
Lee, J.5
-
21
-
-
76749111585
-
Characterizing Flash Memory: Anomalies, Observations, and Applications
-
L. M. Grupp, A. M. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P. H. Siegel and J. K. Wolf. Characterizing Flash Memory: Anomalies, Observations, and Applications. In Proc. of MICRO'09. December 12-16, 2009.
-
Proc. of MICRO'09. December 12-16, 2009
-
-
Grupp, L.M.1
Caulfield, A.M.2
Coburn, J.3
Swanson, S.4
Yaakobi, E.5
Siegel, P.H.6
Wolf, J.K.7
-
24
-
-
84991957861
-
Design Tradeoffs for SSD Performance
-
N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse and R. Panigrahy. Design Tradeoffs for SSD Performance. In Proc. of USENIX'08, June 2008
-
Proc. of USENIX'08, June 2008
-
-
Agrawal, N.1
Prabhakaran, V.2
Wobber, T.3
Davis, J.D.4
Manasse, M.5
Panigrahy, R.6
-
25
-
-
34248527701
-
A multi-channel architecture for high-performance NAND flash-based storage system
-
DOI 10.1016/j.sysarc.2007.01.010, PII S1383762107000045
-
J. Kang, J. Kim, C. Park, H. Park and J. Lee. A multi-channel architecture for high-performance and flash-based storage system. Jounal of Systems Architecture. 53: 644-658, 2007. (Pubitemid 46754996)
-
(2007)
Journal of Systems Architecture
, vol.53
, Issue.9
, pp. 644-658
-
-
Kang, J.-U.1
Kim, J.-S.2
Park, C.3
Park, H.4
Lee, J.5
-
27
-
-
70350295844
-
Design and analysis of flash translation layers for multi-channel NAND flash based storage devices
-
August
-
S. Park, S. Ha, K. Bang and E. Chuang. Design and analysis of flash translation layers for multi-channel NAND flash based storage devices. IEEE Transaction on Consumer Electronics, Vol.55, No.3, August 2009.
-
(2009)
IEEE Transaction on Consumer Electronics
, vol.55
, Issue.3
-
-
Park, S.1
Ha, S.2
Bang, K.3
Chuang, E.4
-
28
-
-
79959605249
-
-
K9XXG08UXA datasheet. http://www.samsung.com/products/semiconductor/ flash/technicallinfo/datasheets.htm.
-
K9XXG08UXA Datasheet
-
-
-
29
-
-
79959618319
-
-
K9NCG08U5M datasheet. http://www.samsung.com/products/semiconductor/ flash/technicallinfo/datasheets.htm.
-
K9NCG08U5M Datasheet
-
-
-
36
-
-
79959603131
-
-
revision 2.0
-
Application note for nand flash memory (revision 2.0) http://www.samsung.com/global/business/semiconductor/products/flash/downloads/ applicationnote/app-nand.pdf
-
Application Note for Nand Flash Memory
-
-
-
37
-
-
77957850342
-
-
revision2.2.http://onfi.org/wp-content/uploads/2009/02/ ONFI%202-2%20 Gold.pdf
-
Open NAND Flash Interface SpecificaRion. revision2.2.http://onfi.org/wp- content/uploads/2009/02/ ONFI%202-2%20 Gold.pdf
-
Open NAND Flash Interface SpecificaRion
-
-
-
43
-
-
27344441029
-
Algorithms and Data Structures for Flash Memories
-
June
-
E. Fal and S. Toledo. Algorithms and Data Structures for Flash Memories. ACM Computing Surveys, Vol.37, No.2, June 2005, pp.138-163.
-
(2005)
ACM Computing Surveys
, vol.37
, Issue.2
, pp. 138-163
-
-
Fal, E.1
Toledo, S.2
-
44
-
-
33746728399
-
System Software for Flash Memory: A Survey
-
International Federation for Information Processing 2006. EUC 2006
-
T. Chung, D. Park, S. Park, D. Lee, S. Lee and H. Song. System Software for Flash Memory: A Survey. International Federation for Information Processing 2006. EUC 2006, LNCS 4096, pp. 394-404. 2006.
-
(2006)
LNCS
, vol.4096
, pp. 394-404
-
-
Chung, T.1
Park, D.2
Park, S.3
Lee, D.4
Lee, S.5
Song, H.6
-
46
-
-
79959619138
-
-
Technical Note TN-29-42
-
Weal-Leveling Techniques in NAND Flash Devices. Technical Note TN-29-42. http://download.micron.com/pdf/technotes/nand/tn2942-nand-wear-leveling.pdf
-
Weal-Leveling Techniques in NAND Flash Devices
-
-
|