A multi-channel architecture for high-performance NAND flash-based storage system

Journal of Systems Architecture

Volumn 53, Issue 9, 2007, Pages 644-658

  Kang, Jeong Uk ^a   Kim, Jin Soo ^a   Park, Chanik ^b   Park, Hyoungjun ^b   Lee, Joonwon ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

I O parallelism; NAND flash memory; Storage system

Indexed keywords

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; NAND CIRCUITS; OPTIMIZATION;

I/O PARALLELISM; MEMORY CHIPS; NAND FLASH MEMORY; STORAGE SYSTEMS;

FLASH MEMORY;

EID: 34248527701     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2007.01.010     Document Type: Article

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