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Volumn 109, Issue , 2013, Pages 117-119
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Barrier engineering for double layer CVD graphene tunnel FETs
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Author keywords
Barrier engineering; Graphene; Tunnel FET
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Indexed keywords
ATOMIC LAYER DEPOSITED;
BARRIER ENGINEERING;
HIGH-K DIELECTRIC;
SEEDING LAYERS;
SUBTHRESHOLD SWING;
TEMPERATURE-DEPENDENT MEASUREMENTS;
TUNNEL FET;
TUNNEL TRANSISTORS;
ATOMIC LAYER DEPOSITION;
FIELD EFFECT TRANSISTORS;
GRAPHENE;
TUNNELS;
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EID: 84876768656
PISSN: 01679317
EISSN: None
Source Type: Journal
DOI: 10.1016/j.mee.2013.02.090 Document Type: Article |
Times cited : (8)
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References (10)
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