Development of wafer level underfill materials and assembly processes for fine pitch Pb-free solder flip chip packaging

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1015-1022

  Nah, Jae Woong ^a   Gaynes, Michael A ^a   Feger, Claudius ^a   Katsurayama, Satoru ^b   Suzuki, Hiroshi ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Sumitomo Bakelite Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY PROCESS; BONDING PROCESS; COOLING CYCLE; ELECTRICAL INTERCONNECTS; ENVIRONMENTAL STRESS; FINE PITCH; FLIP CHIP; FLIP CHIP BONDING; FLIP CHIP SOLDER JOINTS; FLIP-CHIP PACKAGING; FOUR-WIRE; HIGH TEMPERATURE STORAGE; PB FREE SOLDERS; PB-FREE; PB-FREE SOLDER BUMP; POST-CURE; PROCESS DEVELOPMENT; RELIABILITY TEST; RESISTANCE MEASUREMENT; ROOM TEMPERATURE; SCANNING ACOUSTIC MICROSCOPY; SN-AG SOLDER; SOLDER BUMP; TEMPERATURE RAMPING; TEST CHIPS; TEST VEHICLE; THERMAL CYCLE; UNDERFILL MATERIALS; UNDERFILLS; VOID FORMATION; VOID-FREE; WAFER LEVEL;

ASSEMBLY; CONTACT RESISTANCE; CURING; ELECTRIC RESISTANCE MEASUREMENT; PACKAGING MATERIALS; SOLDERING; SOLDERING ALLOYS; SUBSTRATES; WAFER BONDING;

CHIP SCALE PACKAGES;

EID: 79960386402     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898634     Document Type: Conference Paper

References (6)

1. th Electrical components and Technology Conference, Las Vegas, NV, June 2009, pp. 1502-1505.
2. Liu, Y. et al., "Process optimization of lead-free waferlevel underfill material used in chip scale packaging", IEEE international symposium on Advanced Packaging Meterials, March 2005, pp. 293-297.
3. Zhang, Zhuqing et al., "Assembly of Lead-free Bumped Flip-Chip with No-Flow underfills", IEEE Transactions on Electronic Packaging Manufacturing, Vol. 25, No. 2, April 2002, pp. 113-119.
4. Lee, Sangil et al., "Void Formation Study of Flip Chip in Package Using No-Flow Underfill", IEEE Transactions on Electronic Packaging Manufacturing, Vol. 31, No. 4, October 2008, p. 297.
5. Feger, Claudius and LaBianca, Nancy, "Wafer-level underfill process using over-bump-applied resin", US patent published No. 2009/0108472.
6. Katsurayama, S., Suzuki, H. Nah, J-W., Gaynes, M., and Feger C., "High performance wafer level underfill material with high filler loading", proceedings of IEEE 61st Electrical components and Technology Conference, session 9, Orlando, FL, June 2011.