A 32 nm 0.58-fJ/Bit/Search 1-GHz ternary content addressable memory compiler using silicon-aware early-predict late-correct sensing with embedded deep-trench capacitor noise mitigation

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 4, 2013, Pages 932-939

  Arsovski, Igor ^a   Hebig, Travis ^a   Dobson, Daniel ^a   Wistort, Reid ^a  

^a IBM   (United States)

Author keywords

deep trench; early predict late correct; high performance; low power; noise; NOR; sensing; silicon aware; TCAM

Indexed keywords

DEEP-TRENCH; EARLY-PREDICT LATE-CORRECT; HIGH PERFORMANCE; LOW POWER; NOISE; NOR; SENSING; SILICON-AWARE; TCAM;

ENERGY EFFICIENCY; LOGIC GATES; PROGRAM COMPILERS; SILICON; TUNGSTEN;

FORECASTING;

EID: 84875722916     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2239092     Document Type: Article

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