Area-efficient near-associative memories on FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2013, Pages 191-200

  Dhawan, Udit ^a   DeHon, André ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

associative memory; BRAM; cache; CAM; FPGA; hashing

Indexed keywords

AREA OVERHEAD; AREA REDUCTION; AREA-EFFICIENT; ASSOCIATIVE MEMORIES; BENCHMARK PROGRAMS; BRAM; CACHE; DATA CACHES; HASH SCHEME; HASHING; LOW LATENCY; MEMORY RESOURCES; OVERHEAD COSTS; PROPOSED ARCHITECTURES;

ASSOCIATIVE PROCESSING; CAMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MEMORY ARCHITECTURE;

ASSOCIATIVE STORAGE;

EID: 84874508341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2435264.2435298     Document Type: Conference Paper

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