OpenMP-based synergistic parallelization and HW acceleration for on-chip shared-memory clusters

Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

Volumn , Issue , 2012, Pages 751-758

  Burgio, Paolo ^a,b   Marongiu, Andrea ^a   Heller, Dominique ^b   Chavet, Cyrille ^b   Coussy, Philippe ^b   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b UNIVERSITÉ DE BRETAGNE SUD   (France)

Author keywords

design flow; HW acceleration; MPSoCs; OpenMP; Shared memory clustered architectures

Indexed keywords

CLUSTERED ARCHITECTURES; COMMUNICATION COST; DESIGN FLOWS; HARDWARE ACCELERATORS; INTEGRATED APPROACH; MPSOCS; ON CHIPS; OPENMP; PARALLELIZATIONS; PROCESSING CORE; PROGRAMMING MODELS; RUNTIMES; SHARED MEMORIES; TIGHTLY-COUPLED; ZERO-COPY;

APPLICATION PROGRAMMING INTERFACES (API); COMMUNICATION; COMPUTER ARCHITECTURE; DESIGN; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS;

ACCELERATION;

EID: 84872969670     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2012.97     Document Type: Conference Paper

References (25)

1. P.Biswas et al. Introduction of Architecturally Visible Storage in Instruction Set Extensions. Computer-Aided Design of Integrated Circuits and Systems, 2007
2. T.Kluter et al. Speculative DMA for architecturally visible storage in instruction set extensions CODES+ISSS, 2008
3. T.Kluter et al. Way Stealing: Cache-assisted automatic Instruction Set Extensions. 46th ACM/IEEE Design Automation Conference (DAC) '09.
4. N. Goulding-Hotta et al. The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future. Micro, IEEE , vol.31, no.2, 2011
5. G. Venkatesh et al., Conservation cores: reducing the energy of mature computations. In Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems, New York, NY, 2010. ACM.
6. Kronos Group. The OpenCL 1.1 Specifications. http://www.khronos.org/ registry/cl/specs/opencl-1.1.pdf , 2010.
7. The Portland Group. PGI Acceleration Programming Model.http://www.pgroup. com/lit/whitepapers/pgi-accel-prog-model-1.3.pdf , 2010.
8. E. Ayguadé et al. Extending OpenMP to Survive the Heterogeneous Multi-Core Era. In International Journal of Parallel Programming, 38:440-459, 2010.
9. Synopsys. Processor Designer. http://www.synopsys.com/Systems/ BlockDesign/ProcessorDev/Pages/default.aspx.
10. Tensilica. Xtensa Customizable Processors. http://www.tensilica.com/ products/xtensa-customizable.htm.
11. Y. Leow et al. Generating hardware from OpenMP programs. In Field Programmable Technology, 2006. IEEE International Conference on.
12. T. Beatty et al. An OpenMP-based circuit design tool: Customizable bit-width. In Communications, Computers and Signal Processing, 2009.
13. P. Dziurzanski et al. A system for transforming an ANSI C code with OpenMP directives into a SystemC description. In Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.
14. D. Cabrera et al. OpenMP extensions for FPGA accelerators. In Proceedings of the 9th international conference on Systems, architectures, modeling and simulation, Piscataway, NJ, 2009. IEEE Press.
15. T. Hall and K. Kent. A Hardware/Software Co-specification Methodology for Multiple Processor Custom Hardware Devices Based On OpenMP. In Proceedings of the 2008 Research Exposition, 2008.
16. Plurality Ltd. The HyperCore Processor. http://www.plurality.com/ hypercore.html.
17. L. Benini, E. Flamand, and D. Melpignano. P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator. In Design, Automation Test in Europe Conference Exhibition 2012
18. NVIDIA. Next Generation CUDA Compute Architecture: Fermi - WhitePaper. http://www.nvidia.com/content/PDF/fermi-white-papers/NVIDIA-Fermi-Compute- Architecture-Whitepaper.pdf , 2010.
19. Tilera Corp. Product Brief. Tilepro64 processor. 2008
20. A. Rahimi et al. A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. In Design, Automation Test in Europe Conference Exhibition 2011.
21. www.openmp.org. OpenMP Application Program Interface v.3.0. http://www.openmp.org/mp-documents/spec30.pdf
22. GOMP - An OpenMP implementation for GCC. http://gcc.gnu.org/projects/ gomp/.
23. Université de Bretagne-Sud. GAUT HLS Tool. http://www-labsticc. univ-ubs.fr/www-gaut/publications/gaut-flyer.pdf , 1993.
24. L. Benini, D. Bertozzi et al. MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. In Journal of VLSI Signal Processing , Volume 41, Nr. 2, 2005
25. AMD Inc. Fusion series. http://www.amd.com/us/products/technologies/ fusion/Pages/fusion.aspx.