Variation-and-aging aware low power embedded SRAM for multimedia applications

International System on Chip Conference

Volumn , Issue , 2012, Pages 21-26

  Gong, Na ^a   Jiang, Shixiong ^a   Challapalli, Anoosha ^a   Panesar, Manpinder ^a   Sridhar, Ramalingam ^a  

^a UNIVERSITY AT BUFFALO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGING EFFECTS; CMOS TECHNOLOGY; GRACEFUL DEGRADATION; HIGH VOLTAGE; LOW POWER EMBEDDED SRAM; MPEG-4 VIDEO; MULTIMEDIA APPLICATIONS; POWER EFFICIENCY; PROCESS VARIATION; SRAM DESIGN; VIDEO QUALITY; VOLTAGE-SCALING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; LOGIC DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 84872592415     PISSN: 21641676     EISSN: 21641706     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2012.6398371     Document Type: Conference Paper

References (10)

1. MPEG [Online]. Available: http://www.mpeg4.org
2. I. Chang, D. Mohapatra, and K. Roy, "A priority-based 6T/8T hybrid SRAM architecture for aggressive voltage scaling in video applications" IEEE Trans. Circuits Syst. Video Technol., vol. 21, no. 2, pp. 101-112, Feb. 2011.2.
3. Masood Qazi, Mahmut E. Sinangil, and Anantha P. Chandrakasan, "Challenges and Directions for Low-Voltage SRAM" IEEE Design & Test of Computers, vol. 28, no. 1, pp: 32-43, Jan. 2011.
4. Jinmo Kwon, Insoo Lee, and Jongsun Park, "Heterogeneous SRAM Cell Sizing for Low Power H.264 Applications," IEEE Transactions on Circuits and Systems I (TCAS I), vol. 99, no. 2, pp. 1-10, Feb. 2012.4.
5. Minki Cho, Jason Schlessman, Wayne Wolf, and Saibal Mukhopadhyay, "Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications" IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 1, pp. 161-165, Jan. 2011.
6. FreePDK45. Available: http://www.eda.ncsu.edu/wiki/FreePDK45
7. Fahad Ahmed and Linda Milor, "NBTI Resistant SRAM Design", In Proc. IWASI, 2011, pp. 82-87.
8. Sang Park, Kaushik Roy, and Kunhyuk Kang, "Reliability Implications of Bias-Temperature Instability in Digital ICs", IEEE Design & Test of Computers, pp.8-17, Dec. 2009.
9. Jiajing Wang and Benton H. Calhoun, "Minimum Supply Voltage and Yield Estimation for Large SRAMs Under parametric Variations", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 1, pp. 2120-2125, Jan. 2011.
10. MOSIS deep design rules. http://www.mosis.com