Reconfigurable SRAM architecture with spatial voltage scaling for low power mobile multimedia applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 1, 2011, Pages 161-165

  Cho, Minki ^a   Schlessman, Jason ^b   Wolf, Wayne ^a   Mukhopadhyay, Saibal ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b PRINCETON UNIVERSITY   (United States)

Author keywords

Image processing; Low power; multimedia; process variations; reconfiguration; SRAM

Indexed keywords

LOW POWER; MULTIMEDIA; PROCESS VARIATION; RECONFIGURATION; SRAM;

IMAGE QUALITY; IMAGING SYSTEMS;

STATIC RANDOM ACCESS STORAGE;

EID: 78650871041     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2031468     Document Type: Article

References (12)

1. S. Yang et al., "Power and performance analysis of motion estimation based on hardware and software realizations," IEEE Trans. Computers, vol. 54, no. 6, pp. 714-716, Jun. 2005.
2. G. Chen and M. Kandemir, "Optimizing address code generation for array-intensive DSP applications," in Proc. Int. Symp. Code Generation Optimization, 2005, pp. 141-152.
3. S. Mukhopadhyay et al., "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nano-scaled CMOS," IEEE Trans. Comput.-Aided Design, vol. 24, no. 5, pp. 1859-1880, Dec. 2005.
4. F. Kurdahi et al., "Error aware design," in Proc. 10th Eur. Conf. Digital System Design Architectures, Aug. 2007, pp. 8-15.
5. A. K. Djahromi et al., "Cross layer error exploitation for aggressive voltage scaling," in Proc. IEEE Int. Symp. Quality Electronic Design, Mar. 2007, pp. 192-197.
6. J. George, B. Marr, B. E. S. Akgul, and K. V. Palem, "Probabilistic arithmetic and energy efficient embedded signal processing," in Proc. CASES, Oct. 2006, pp. 168-198.
7. K. Yi, S. Y. Cheng, F. Kurdahi, and A. Ettawil, "A partial memory protection scheme for higher effective yield of embedded memory for video data," in Proc. ACSAC, 2008, pp. 273-278.
8. M. Cho, J. Schlessman, W. Wolf, and S. Mukhopadhyay, "Accuracyaware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications," in Proc. ASPDAC, 2009, pp. 823-828.
9. K. Zhang, V. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y.Wang, B. Zheng, and M. Bohr, "A 3-GHz 70 MB SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply," in Proc. ISSCC 2005, pp. 474-611.
10. [Online]. Available: http://www.imageprocessingplace.com/
11. Z. Wang, A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli, "Image quality assessment: From error visibility to structural similarity," IEEE Trans. Image Process., vol. 13, no. 4, pp. 600-612, Apr. 2004.
12. T. Liu, T. Lin, S. Wang, W. Lee, J. Yang, K. Hou, and C. Lee, "A 125 uW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 161-169, Jan. 2007.