Reliability implications of bias-temperature instability in digital ICs

IEEE Design and Test of Computers

Volumn 26, Issue 6, 2009, Pages 8-17

  Park, Sang Phill ^a   Roy, Kaushik ^a   Kang, Kunhyuk ^b  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AC STRESS; BIAS TEMPERATURE INSTABILITY; CIRCUIT APPLICATION; DEGRADATION PROCESS; HIGH TEMPERATURE; MEMORY ARRAY; NEGATIVE BIAS; OPERATING TEMPERATURE; PERFORMANCE DEGRADATION; READ STABILITY; SIMULATION RESULT; SRAM CELL; STANDARD CELL; STATIC NOISE MARGIN; STATIC TIMING ANALYSIS; TEMPERATURE STRESS;

DEGRADATION; DELAY CIRCUITS; ELECTRIC BATTERIES; INTEGRATED CIRCUITS; NEGATIVE TEMPERATURE COEFFICIENT; STATIC RANDOM ACCESS STORAGE; SWITCHING CIRCUITS; THERMODYNAMIC STABILITY; TIMING CIRCUITS;

LOGIC CIRCUITS;

EID: 73249136320     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2009.154     Document Type: Article

References (13)

1. D. K. Schroder and J. A. Babcock, "Negative Bias Temperature Instability: Road to Cross in Deep Submicron Silicon Semiconductor Manufacturing", J. Applied Physics, vol. 94, no. 1, 2003, pp. 1-18.
2. D. Varghese et al., "On the Dispersive versus Arrhenius Temperature Activation of NBTI Time Evolution in Plasma Nitrided Gate Oxides: Measurements, Theory, and Implications", Proc. IEEE Int'l Electronic Devices Meeting (IEDM 05), IEEE Press, 2005, pp. 684-687.
3. A. T. Krishnan et al., "Material Dependence of Hydrogen Diffusion: Implications for NBTI Degradation", Proc. IEEE Int'l Electronic Devices Meeting (IEDM 05), IEEE Press
4. 2005, pp. 688-691.
5. M. A. Alam, "A Critical Examination of the Mechanics of Dynamic NBTI for PMOSFETs", Proc. IEEE Int'l Electronic Devices Meeting (IEDM 03), IEEE Press, 2003, pp. 14.4.1-14.4.4.
6. G. La Rosa et al., "Impact of NBTI Induced Statistical Variation to SRAM Cell Stability", Proc. 44th Ann. IEEE Int'l Reliability Physics Symp. (IRPS 06), IEEE Press
7. 2006, pp. 274-282.
8. K. Kang et al., "NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution?" Proc. Asia and South Pacific Design Automation Conf. (ASPDAC 07), IEEE CS Press, 2007, pp. 726-731.
9. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "NBTI-Aware Synthesis of Digital Circuits", Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 370-375.
10. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "An Analytical Model for Negative Bias Temperature Instability", Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), ACM Press, 2006, pp. 493-496.
11. I. J. Chang et al., "Fast and Accurate Estimation of Nanoscaled SRAM Read Failure Probability Using Critical Point Sampling", Proc. IEEE Custom Integrated Circuits Conf. (CICC 05), IEEE Press, 2005, pp. 439-442.
12. H. Kufluoglu and M. A. Alam, "Theory of Interface-Trap-Induced NBTI Degradation for Reduced Cross Section MOSFETs", IEEE Trans. Electron Devices, vol. 53, no. 5, 2006, pp. 1120-1130.
13. A. S. Oates, "Reliability Issues for High-k Gate Dielectrics", Proc. IEEE Int'l Electron Devices Meeting (IEDM 03), IEEE Press, 2003, pp. 38.2.1-38.2.4.