NBTI resistant SRAM design

Proceedings of the 4th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2011

Volumn , Issue , 2011, Pages 82-87

  Ahmed, Fahad ^a   Milor, Linda ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

cache; fault prediction; NBTI monitoring; reliability; SRAM cell; stability analysis

Indexed keywords

6T-SRAM; CACHE; DEVICE DEGRADATION; DEVICE OPERATIONS; ELECTRICAL FIELD; FAULT PREDICTION; MEMORY REDUNDANCY; NEGATIVE BIAS TEMPERATURE INSTABILITY; ON CHIPS; OPERATING TEMPERATURE; PMOS DEVICES; PROCESS VARIATION; SRAM CELL; SRAM DESIGN; STABILITY ANALYSIS; TECHNOLOGY NODES;

CELLS; DEGRADATION; INTEGRATED CIRCUITS; LOGIC DESIGN; RELIABILITY; SENSORS; THERMODYNAMIC STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 80052890146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWASI.2011.6004692     Document Type: Conference Paper

References (12)

1. DDQ", in Proc. IEEE Int. Test Conference, 2007, pp. 1-10.
2. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "Impact of NBTI on SRAM read stability and design for reliability", in Proc. Int. Symp. Quality Electronic Design, 2006, pp. 213-218.
3. V. Huard, et al., "NBTI degradation: From transistor to SRAM arrays", in Proc. IEEE Int. Reliability Physics Symposium, 2008, pp. 289-300.
4. A. Haggag, et al, "Understanding SRAM high-temperatureoperating-life NBTI: Statistics and permanent vs. recoverable damage", Proc. Int. Reliability Physics Symp., 2007, pp. 452-456.
5. M. Alam and S. Mahapatra, "A comprehensive model of PMOS NBTI degradation", Microelectronics Reliability, vol. 45, pp. 71-81, 2005.
6. W. Wenping, et al., "An efficient method to identify critical gates under circuit aging", in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, 2007, pp. 735-740.
7. M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for PMOSFETs", in Proc. IEEE Int. Electron Devices Meeting, 2003, pp. 14.4.1-14.4.4.
8. J. G. Skellam, "The frequency distribution of the difference between two Poisson variates belonging to different populations", J. of Royal Statistical Society, A, vol. 109, no. 3, p. 296, 1946.
9. S. Rauch, "Review and reexamination of reliability effects related to NBTI-induced statistical variations", IEEE Trans. Device and Materials Reliability, vol. 7, no. 4, pp. 524-530, Dec. 2007.
10. P. Sangwoo, et al", Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies", IEEE Trans, on Device and Materials Reliability, vol. 8, pp. 519-525, 2008.
11. A. J. Bhavnagarwala, et al., "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", IEEE J. of Solid-State Circuits, vol. 36, pp. 658-665, 2001. (Pubitemid 32407171)
12. F. Ahmed and L. Milor, "Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST", in Proc. VLSI Test Symp., 2010, pp. 63-68.