Low-temperature electrical characterization of junctionless transistors

Solid-State Electronics

Volumn 80, Issue , 2013, Pages 135-141

  Jeon, Dae Young ^a,c   Park, So Jeong ^a,c   Mouis, Mireille ^a   Barraud, Sylvain ^b   Kim, Gyu Tae ^c   Ghibaudo, Gérard ^a  

^a IMEP LAHC   (France)

^b CEA LETI   (France)

^c Korea University   (South Korea)

Author keywords

Flat band voltage (Vfb); Implantation induced defects; Junctionless transistors (JLTs); Scattering mechanisms; Threshold voltage (Vth)

Indexed keywords

DEFECTS INDUCED; ELECTRICAL CHARACTERIZATION; ELECTRICAL PERFORMANCE; FLAT-BAND VOLTAGE; GATE LENGTH; IMPLANTATION-INDUCED DEFECTS; JUNCTIONLESS; LOW FIELD MOBILITY; LOW TEMPERATURES; NEUTRAL DEFECTS; PLANAR STRUCTURE; SCATTERING MECHANISMS; SUBTHRESHOLD SWING; TEMPERATURE DEPENDENCE;

DEFECTS; SCATTERING; TEMPERATURE; THRESHOLD VOLTAGE;

TRANSISTORS;

EID: 84871651510     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2012.10.018     Document Type: Article

References (19)

1. J.P. Colinge, C.W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, and I. Ferain Nanowire transistors without junctions Nat Nanotechnol 5 2010 225 229
2. A.M. Ionescu Electronic devices: nanowire transistors made easy Nat Nanotechnol 5 2010 178 179
3. g down to 26 nm Electron Device Lett IEEE 32 2011 1170 1172
4. J.P. Colinge, C.W. Lee, I. Ferain, N.D. Akhavan, R. Yan, and P. Razavi Reduced electric field in junctionless transistors Appl Phys Lett 96 2010 073510
5. Jeon D-Y, Park SJ, Mouis M, Berthome M, Barraud S, Kim G-T, Ghibaudo G. Electrical characterization and revisited parameter extraction methodology in junctionless transistors. In: Proceedings of EuroSOI conference, Montpellier, France; 2012. p. 109-10.
6. J.T. Park, J.Y. Kim, C.W. Lee, and J.P. Colinge Low-temperature conductance oscillations in junctionless nanowire transistors Appl Phys Lett 97 2010 172101
7. M. de Souza, M.A. Pavanello, R.D. Trevisoli, R.T. Doria, and J.P. Colinge Cryogenic operation of junctionless nanowire transistors IEEE Electron Device Lett 32 2011 1322 1324
8. F. Balestra, and G. Ghibaudo Brief review of the MOS device physics for low temperature electronics Solid State Electron 37 1994 1967 1975 (Pubitemid 124017182)
9. D.S. Jeon, and D.E. Burk MOSFET electron inversion layer mobilities-a physically based semi-empirical model for a wide temperature range IEEE Trans Electron Device 36 1989 1456 1463
10. D.K. Schroder Semiconductor material and device characterization 2006 Wiley-IEEE press
11. I. Filanovsky, and A. Allam Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits IEEE Trans Circuit Syst I: Fund Theory Appl 48 2001 876 884 (Pubitemid 32694330)
12. J.M. Sallese, N. Chevillon, C. Lallement, B. Iniguez, and F. Pregaldiny Charge-based modeling of junctionless double-gate field-effect transistors IEEE Trans Electron Dev 2011 1 10
13. R.S. Muller, T.I. Kamins, and M. Chan Device electronics for integrated circuits 2003 Wiley
14. T. Poiroux, F. Andrieu, O. Weber, C. Fenouillet-Béranger, C. Buj-Dufournet, and P. Perreau Ultrathin body silicon on insulator transistors for 22 nm node and beyond Semicon Insul Mater Nanoelectronics Appl 2011 155 168
15. M. Mouis, and G. Ghibaudo Accurate determination of transport parameters in sub-65nm MOS transistors Nanoscale CMOS: Innovative Materials Modeling and Characterization 2010 Wiley New York, USA June, Chapter 14, ISBN: 978-1-84821-180-3
16. C. Jacoboni, C. Canali, G. Ottaviani, and A. Alberigi Quaranta A review of some charge transport properties of silicon Solid State Electron 20 1977 77 89
17. Ghibaudo G. Mobility Characterization in Advanced FD-SOI CMOS Devices, Semiconductor-On-Insulator Materials for Nanoelectronics Applications; 2011. p. 307-22.
18. 2 channel properties in SOI MOSFETs IEEE Electron Device Lett 30 2009 1075 1077
19. Cros A, Romanjek K, Fleury D, Harrison S, Cerutti R, Coronel P, et al. Unexpected mobility degradation for very short devices: a new challenge for CMOS scaling, IEDM; 2006. p. 1-4.