-
1
-
-
33748554808
-
Ultra-low voltage minimum-energy CMOS
-
July
-
S. Hanson, et al., "Ultra-Low Voltage Minimum-Energy CMOS," IBM Journal of Research and Development, Volume 50 Issue 4/5, July 2006.
-
(2006)
IBM Journal of Research and Development
, vol.50
, Issue.4-5
-
-
Hanson, S.1
-
2
-
-
34347222026
-
Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing
-
J. Keane, et al., "Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing," In Proeedings of 43rd ACM/IEEE Design Automation Conference, pp. 425-428, 2006.
-
(2006)
Proeedings of 43rd ACM/IEEE Design Automation Conference
, pp. 425-428
-
-
Keane, J.1
-
3
-
-
34347237842
-
Utilizing reverse short-channel effect for optimal subthreshold circuit design
-
T. H. Kim, et al., "Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design," IEEE Trans. VLSI Syst. 15(7), pp. 821-829, 2007.
-
(2007)
IEEE Trans. VLSI Syst.
, vol.15
, Issue.7
, pp. 821-829
-
-
Kim, T.H.1
-
4
-
-
80052678334
-
A 40 nm inverse-narrow-width-effect-aware subthreshold standard cell library
-
J. Zhou, et al., "A 40 nm inverse-narrow-width-effect-aware subthreshold standard cell library," DAC, pp. 441-446. 2011.
-
(2011)
DAC
, pp. 441-446
-
-
Zhou, J.1
-
5
-
-
84856355795
-
A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques
-
N. Reynders and W. Dehaene, "A 190mV supply, 10MHz, 90nm CMOS, Pipelined Sub-Threshold Adder using Variation-Resilient Circuit Techniques," ASSCC, pp. 113-116, 2011.
-
(2011)
ASSCC
, pp. 113-116
-
-
Reynders, N.1
Dehaene, W.2
-
6
-
-
79955721005
-
A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logic
-
N. Lotze, et al. ,"A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logic," ISSCC, pp. 340-342, 2011.
-
(2011)
ISSCC
, pp. 340-342
-
-
Lotze, N.1
-
7
-
-
84932103562
-
Characterizing and modeling minimum energy operation for subthreshold circuits
-
B. Calhoun and A. Chandrakasan, "Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits," ISLPED 2004.
-
(2004)
ISLPED
-
-
Calhoun, B.1
Chandrakasan, A.2
-
8
-
-
34247202065
-
Variation-driven device sizing for minimum energy sub-threshold circuit
-
J. Kwong and A. Chandrakasan, "Variation-Driven Device Sizing for Minimum Energy Sub-Threshold Circuit," ISLPED 2006: 8-13.
-
(2006)
ISLPED
, pp. 8-13
-
-
Kwong, J.1
Chandrakasan, A.2
-
9
-
-
80054973809
-
Process variation reduction for CMOS logic operating at sub-threshold supply voltage
-
Bo Liu, et al., "Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage", DSD 2011: 135-139.
-
(2011)
DSD
, pp. 135-139
-
-
Liu, B.1
-
10
-
-
0036858210
-
Adaptive body bias for reducing impacts of dieto-die and within-die parameter variations on microprocessor frequency and leakage
-
Nov
-
J.W. Tschanz, et al. , "Adaptive body bias for reducing impacts of dieto-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid-State Circuits, vol.37, no.11, pp. 1396-1402, Nov 2002.
-
(2002)
IEEE Journal of Solid-State Circuits
, vol.37
, Issue.11
, pp. 1396-1402
-
-
Tschanz, J.W.1
-
11
-
-
0003479594
-
Circuits, interconnections, and packaging for VLSI
-
Addison-Wesley
-
H. B. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI," Reading, Addison-Wesley, 1990.
-
(1990)
Reading
-
-
Bakoglu, H.B.1
-
13
-
-
0030416122
-
Effects of metal coverage on MOSFET matching
-
H. Tuinhout et al., "Effects of Metal Coverage on MOSFET Matching," IEDM, pp. 735-8, 1996.
-
(1996)
IEDM
, pp. 735-8
-
-
Tuinhout, H.1
-
14
-
-
3042739407
-
Design optimization of low-power high-performance DSP building blocks
-
T. Gemmeke, M. Gansen, H.J. Stockmanns, T.G. Noll, "Design optimization of low-power high-performance DSP building blocks," IEEE Journal of Solid-State Circuits, vol.39, no.7, pp. 1131-1139, 2004.
-
(2004)
IEEE Journal of Solid-State Circuits
, vol.39
, Issue.7
, pp. 1131-1139
-
-
Gemmeke, T.1
Gansen, M.2
Stockmanns, H.J.3
Noll, T.G.4
|