A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

Volumn , Issue , 2011, Pages 113-116

  Reynders, Nele ^a   Dehaene, Wim ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ADDER DESIGN; CIRCUIT TECHNIQUES; ENERGY DELAY PRODUCT; NOISE MARGINS; OPTIMAL SIZING; SUBTHRESHOLD; TIME BORROWING; TRANSMISSION-GATE LOGIC;

CMOS INTEGRATED CIRCUITS; ENERGY UTILIZATION;

ADDERS;

EID: 84856355795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2011.6123617     Document Type: Conference Paper

References (7)

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4. D. Harris, Skew-Tolerant Circuit Design. Morgan Kaufmann Publ., 2001.
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7. O. Weiss, M. Gansen, and T. Noll, "A flexible datapath generator for physical oriented design," in ESSCIRC, Sep. 2001, pp. 393-396.