Process variation reduction for CMOS logic operating at sub-threshold supply voltage

Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

Volumn , Issue , 2011, Pages 135-139

  Liu, Bo ^a   Pourshaghaghi, Hamid Reza ^a   Londoño, Sebastian Moreno ^a   De Gyvez, José Pineda ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Body biasing; Fuzzy logic; Pipeline; Process variation; Sub threshold

Indexed keywords

ADAPTIVE FUZZY LOGIC CONTROLLER; BODY BIAS; BODY BIASING; BUILDING ENERGY; CIRCUIT DESIGNS; CMOS LOGIC; DRIVING CURRENT; ENERGY EFFICIENT; PERFORMANCE DEGRADATION; POST-SILICON; PROCESS VARIATION; PROCESS VARIATION REDUCTION; SUBTHRESHOLD; SUPPLY VOLTAGES;

DEGRADATION; DESIGN; DIGITAL CIRCUITS; ENERGY EFFICIENCY; FUZZY LOGIC; FUZZY SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; SENSITIVITY ANALYSIS; SYSTEMS ANALYSIS;

LOGIC CIRCUITS;

EID: 80054973809     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2011.21     Document Type: Conference Paper

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