A linear algebra core design for efficient level-3 BLAS

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2012, Pages 149-152

  Pedram, Ardavan ^a   Gilani, Syed Zohaib ^b   Kim, Nam Sung ^b   Geijn, Robert Van De ^c   Schulte, Michael ^d   Gerstlauer, Andreas ^a  

^a The University of Texas at Austin   (United States)

^b University of Wisconsin Madison   (United States)

^c AMD Research ^*  (United States)

^d AMD Research   (United States)

Author keywords

BLAS; Co design; Linear Algebra; Low Power

Indexed keywords

ALGORITHM/ARCHITECTURE CO-DESIGN; BASIC LINEAR ALGEBRA SUBPROGRAMS; BLAS; CMOS TECHNOLOGY; CO-DESIGNS; COMPUTATIONAL KERNELS; CORE DESIGN; DOUBLE PRECISION; LEVEL-3 BLAS; LOW POWER; POWER EFFICIENCY; PROCESSING ELEMENTS;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; LINEAR ALGEBRA; PROGRAM PROCESSORS;

DESIGN;

EID: 84870726245     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2012.18     Document Type: Conference Paper

References (12)

1. R. Hameed et al., "Understanding sources of inefficiency in general-purpose chips," ISCA '10, 2010.
2. A. Pedram et al., "A high-performance, low-power linear algebra core," ASAP '11, pp. 35-41, 2011.
3. K. Goto et al, "High-performance implementation of the level-3 BLAS," ACM Trans. Math. Softw., vol. 35, no. 1, pp. 1-14, 2008.
4. V. Volkov and J. Demmel, "Benchmarking GPUs to tune dense linear algebra," SC 2008, 2008.
5. K. Johnson et al., "General-purpose systolic arrays," Computer, vol. 26, no. 11, pp. 20-31, 1993.
6. J. Kelm et al., "Rigel: an architecture and scalable programming interface for a 1000-core accelerator," ISCA '09, 2009.
7. S. Vangal et al., "An 80-tile sub-100-w teraflops processor in 65-nm cmos," IEEE J. of Solid-State Circuits, vol. 43, no. 1, 2008.
8. L. Zhuo and V. Prasanna, "High-performance designs for linear algebra operations on reconfigurable hardware," IEEE Trans. on Computers, vol. 57, no. 8, 2008.
9. M. Parker, "High-performance floating-point implementation using FPGAs," in MILCOM, 2009.
10. J.-W. Jang et al., "Energy- and time-efficient matrix multiplication on FPGAs," IEEE Trans on VLSI Systems,, vol. 13, no. 11, 2005.
11. S. Gilani et al., "Energy-efficient floating-point arithmetic for software-defined radio architectures," in ASAP2011.
12. N. Muralimanohar et al., "Architecting efficient interconnects for large caches with cacti 6.0," IEEE Micro, vol. 28, pp. 69-79, January 2008.