On evaluating signal selection algorithms for post-silicon debug

Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Volumn , Issue , 2011, Pages 290-296

  Hung, Eddie ^a   Wilton, Steven J E ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Post Silicon Debug; Signal Selection; Trace Buffer

Indexed keywords

FABRICATED CHIPS; INTEGRATED CIRCUIT DESIGNS; POST-SILICON DEBUG; SIGNAL SELECTION; STATE SPACE; SYSTEM STATE; TRACE BUFFER;

ALGORITHMS; INTEGRATED CIRCUIT MANUFACTURE;

DESIGN;

EID: 79959229533     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2011.5770739     Document Type: Conference Paper

References (11)

1. K.H. Chang, I.L. Markov, and V. Bertaco, Automat-ing Post-Silicon Debugging and Repair," in IEEE International Conference on Computer-Aided Design, 2007, pp. 91-98.
2. T.J. Foster, D.L. Lastor, and P. Singh, First Silicon Functional Validation and Debug of Multicore Micro-processors," Very Large Scale Integration Systems, IEEE Trans. on, vol. 15, no. 5, pp. 495-504, May 2007. (Pubitemid 46853317)
3. Mack Riley, Nathan Chelstrom, Mike Genden, and Shoji Sawamura, "Debug of the CELL Processor: Moving the Lab into Silicon " in Test Conference, 2006. ITC '06. IEEE Intl., Oct. 2006, pp. 1-9.
4. B.R. Quinton, A.M. Hughes, and S.J.E. Wilton, Post-Silicon Debug of Complex Multi Clock and Power Domain ICs," in IEEE International Workshop on Silicon Debug and Diagnosis, 2010.
5. Ho Fai Ko and Nicola Nicolici, Algorithms for State Restoration and Trace-Signal Selection for Data Ac-quisition in Silicon Debug Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, no. 2, pp. 285-297, 2009.
6. Xiao Liu and Qiang Xu, Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation in Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 1338-1343.
7. Joon-Sung Yang and N.A. Touba, Automated Selec-tion of Signals to Observe for Efficient Silicon Debug," in VLSI Test Symposium, 2009. VTS '09. 27th IEEE, May 2009, pp. 79-84.
8. Jianliang Gao, Yinhe Han, and Xiaowei Li, A New Post-Silicon Debug Approach Based on Suspect Win-dow," in VLSI Test Symposium, 2009. VTS '09. 27th IEEE, May 2009, pp. 85-90.
9. B. Quinton and S. Wilton, Post-Silicon Debug using Programmable Logic Cores," in Field-Programmable Technology, 2005. Proceed ings. 2005 IEEE Interna-tional Conference on, Dec. 2005, pp. 241-247. (Pubitemid 46170570)
10. Hyunwoo Cho, G.D. Hachtel, E. Macii, M. Poncino, and F. Somenzi, Automatic State Space Decomposi-tion for Approximate FSM Traversal Based on Circuit Analysis Computer-Aided Design of Integrated Cir-cuits and Systems, IEEE Trans. on, vol. 15, no. 12, pp. 1451-1464, Dec 1996. (Pubitemid 126780408)
11. Altera Benchmark Designs For The Quartus Uni-versity Interface Program (QUIP) Version 1.1. http: //www.altera.com/support/software/download/altera- design/quip/quip-download.jsp, 2008.