Improved abstractions and turnaround time for FPGA design validation and debug

Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011

Volumn , Issue , 2011, Pages 518-523

  Iskander, Yousef S ^a   Patterson, Cameron D ^a   Craven, Stephen D ^b  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^b University of Tennessee at Chattanooga   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BREAK-POINTS; FPGA DESIGN; INTERACTIVITY; LEVELS OF ABSTRACTION; REFERENCE MODELS;

ABSTRACTING; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INSPECTION; SOFTWARE TESTING; TURNAROUND TIME;

DESIGN;

EID: 80455158151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2011.102     Document Type: Conference Paper

References (16)

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