Design of the two-core x86-64 AMD "bulldozer" module in 32 nm SOI CMOS

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 1, 2012, Pages 164-176

  McIntyre, Hugh ^a   Arekapudi, Srikanth ^a   Busta, Eric ^a   Fischer, Timothy ^a   Golden, Michael ^a   Horiuchi, Aaron ^a   Meneghini, Tom ^b   Naffziger, Samuel ^a   Vinh, James ^a  

^a ADVANCED MICRO DEVICES   (United States)

^b AMD   (United States)

Author keywords

64 bit architecture; 8T RAMcell; Array design techniques; circuit design; clock power reduction; clocked storage elements; clocks; CMT; design productivity; dynamic circuit design; energy efficient circuits; flip flops; floating point; idle power; low power; low voltage design; multi core; power management; register files; soft errors; SOI; x86 64

Indexed keywords

64-BIT ARCHITECTURES; 8T RAMCELL; ARRAY DESIGN; CIRCUIT DESIGNS; CMT; DESIGN PRODUCTIVITY; DYNAMIC CIRCUITS; ENERGY EFFICIENT; FLIP-FLOPS; FLOATING POINTS; IDLE POWER; LOW POWER; LOW VOLTAGE DESIGN; MULTI CORE; POWER MANAGEMENTS; POWER REDUCTIONS; REGISTER FILES; SOFT ERROR; SOI; STORAGE ELEMENTS; X86-64;

CLOCKS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; ENERGY MANAGEMENT; INTEGRATED CIRCUIT MANUFACTURE; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; OPTIMIZATION;

DESIGN;

EID: 84869232933     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2167823     Document Type: Article

References (9)

1. M. Butler et al., "Bulldozer: An approach to multithreaded compute performance," IEEE Micro, vol. 31, no. 2, pp. 6-15, Mar./Apr. 2011.
2. T. Fischer et al., "Design solutions for the Bulldozer 32 nm SOI 2-core processor module in an 8-core CPU," presented at the IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 2011.
3. M. Golden et al., "40-entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core," presented at the IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 2011.
4. R. Jotwani et al., "An x86-64 core in 32 nm SOI CMOS," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 162-172, Jan. 2011.
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7. Advanced Configuration & Power Interface Specification Rev 4.0a. Apr. 2010 [Online]. Available: http://www.acpi.info/spec.htm
8. M. Yilmaz et al., "The scan-DFT features of AMD's next-generation microprocessor core," presented at the 2010 Int. Test Conf., Austin, TX, Paper 2.1.
9. P. Restle and A. Deutch, "Designing the best clock distribution network," in 1998 Symp. VLSI Circuits Dig. Papers, 1998, pp. 2-5.