An x86-64 core in 32 nm SOI CMOS

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 162-172

  Jotwani, Ravi ^a   Sundaram, Sriram ^a   Kosonocky, Stephen ^a   Schaefer, Alex ^a   Andrade, Victor F ^a   Novak, Amy ^a   Naffziger, Samuel ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

64 bit architecture; 8T RAMcell; Array design techniques; clock power reduction; electromigration; low power; power gating; power monitor

Indexed keywords

64-BIT ARCHITECTURES; 8T RAMCELL; ARRAY DESIGN; LOW POWER; POWER GATINGS; POWER MONITOR;

ELECTROMIGRATION; GERMANIUM; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

DESIGN;

EID: 78650883336     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2080530     Document Type: Conference Paper

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