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Volumn 53, Issue , 2010, Pages 96-97

Westmere: A family of 32nm IA processors

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OPTIMIZATION; CORE DESIGN; CORE PROCESSORS; DIE AREA; ENCRYPTION/DECRYPTION; METAL-GATE; PROCESS TECHNOLOGIES; SERVER PROCESSORS; VIRTUALIZED ENVIRONMENT;

EID: 77952125596     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434033     Document Type: Conference Paper
Times cited : (70)

References (3)
  • 1
    • 64549151943 scopus 로고    scopus 로고
    • nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171um2 SRAM Cell Size in a 291Mb Array
    • Dec.
    • nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171um2 SRAM Cell Size in a 291Mb Array", IEDM Tech. Digest, Dec. 2008.
    • (2008) IEDM Tech. Digest
    • Natarajan, S.1
  • 3
    • 63449130377 scopus 로고    scopus 로고
    • Next Generation Intel® Core™ Micro-Architecture (Nehalem) Clocking
    • Apr
    • N. Kurd et al., "Next Generation Intel® Core™ Micro-Architecture (Nehalem) Clocking", IEEE J. Solid State Circuits, vol. 44, issue 4, pp. 1121-1129, Apr 2009.
    • (2009) IEEE J. Solid State Circuits , vol.44 , Issue.4 , pp. 1121-1129
    • Kurd, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.