Bulldozer: An approach to multithreaded compute performance

IEEE Micro

Volumn 31, Issue 2, 2011, Pages 6-15

  Butler, Michael ^a   Barnes, Leslie ^a   Sarma, Debjit Das ^a   Gelinas, Bob ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

Bulldozer; microarchitecture implementation considerations; microcomputers; Microprocessors; processor architectures

Indexed keywords

BULLDOZER; FLOATING-POINT MULTIPLY-ACCUMULATE; LEVEL 2; MICRO ARCHITECTURES; MICROARCHITECTURAL LATENCY; MICROARCHITECTURE IMPLEMENTATION CONSIDERATIONS; MICROPROCESSORS; MULTITHREADED; MULTITHREADING ARCHITECTURES; NEW DIRECTIONS; POWER EFFICIENT; PROCESSOR ARCHITECTURES; STRUCTURE SIZES; SUB-BLOCKS;

ARCHITECTURE; COMPUTERS; MICROCOMPUTERS; MICROPROCESSOR CHIPS; MULTITASKING;

COMPUTER ARCHITECTURE;

EID: 79955397043     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2011.23     Document Type: Conference Paper

References (12)

1. T Fischer et al., "Design Solutions for the Bulldozer 32-nm SOI 2-Core Processor Module in an 8-Core CPU," IEEE Int'l Solid State Circuits Conf., IEEE Press, 2011.
2. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded SPARC Processor," IEEE Micro, vol. 25, no. 2, 2005, pp. 21-29. (Pubitemid 40784326)
3. J.D. Davis, J. Laudon, and K. Olukotun, "Maximizing CMP Throughput with Mediocre Cores," Proc. 14th Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2005, pp. 51-62. (Pubitemid 44159727)
4. "Hyper-Threading Technology," Intel Tech. J., vol. 6, no. 1, 2002, pp. 4-15.
5. H.M. Mathis et al., "Characterization of Simultaneous Multithreading (SMT) Efficiency in Power5," IBM J. Research and Development, Jul.-Sep. 2005, pp. 555-564. (Pubitemid 41398404)
6. J. Emer, "Simultaneous Multithreading: Multiplying Alpha Performance," Proc. Microprocessor Forum, Linley Group, 1999.
7. D. Tullsen, S. Eggers, and H. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," Proc. 22nd Ann. Int'l Symp. Computer Architecture, ACM Press, 1995, pp. 392-403.
8. G. Reinman, B. Calder, and T. Austin, "Optimizations Enabled by a Decoupled Front-End Architecture," IEEE Trans. Computers, vol. 50, no. 4, 2001, pp. 338-355. (Pubitemid 32444375)
9. R. Jotwani et al., "An x86, 64-Core Implemented in 32-nm SOI CMOS," IEEE Int'l Solid State Circuits Conf. IEEE Press, 2010, pp. 106-107.
10. AMD64 Architecture Programmers Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions, AMD, 2009.
11. M. Golden et al., "40-Entry Unified Out-of-Order Integer Execution Unit for the AMD Bulldozer x86-64 Core," IEEE Int'l Solid State Circuits Conf., IEEE Press, 2011, pp. 80-81.
12. R.K. Montoye, E. Hokenek, and S.L. Runyon, "Design of the IBM RISC System/6000Floating Point Execution Unit," IBM J. Research and Development, vol. 34, 1990, pp. 59-70. (Pubitemid 20686677)