Design solutions for the bulldozer 32nm SOI 2-core processor module in an 8-core CPU

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 78-79

  Fischer, Tim ^a   Arekapudi, Srikanth ^a   Busta, Eric ^a   Dietz, Carl ^a   Golden, Michael ^a   Hilker, Scott ^a   Horiuchi, Aaron ^a   Hurd, Kevin A ^a   Johnson, Dave ^a   McIntyre, Hugh ^a   Naffziger, Samuel ^a   Vinh, James ^a   White, Jonathan ^b   Wilcox, Kathryn ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b Amd   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; EARTHMOVING MACHINERY;

DESIGN SOLUTIONS; HIGHER FREQUENCIES; INVERTER DELAY; L2 CACHE; MICRO ARCHITECTURES; PROCESSOR MODULES; SOI CMOS;

INTEGRATED CIRCUIT DESIGN;

EID: 79955718277     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746227     Document Type: Conference Paper

References (4)

1. Butler, M. "Bulldozer: A new approach to multithreaded compute performance." Hot Chips 22, August 24, 2010.
2. Jotwani, R. et al. "An x86-64 Core Implemented in 32nm SOI CMOS," ISSCC Dig. Tech. Papers, pp. 106-107, Feb. 2010.
3. Golden, M. et al. "40-entry unified, out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 two-core CPU module", Accepted to ISSCC 2011.
4. Golden, M. et al., "A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support," ISSCC Dig. Tech. Papers, vol. pp. 325-332, Feb. 2006.